How do I configure SPLL CLK?

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How do I configure SPLL CLK?

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jinsheng20
Contributor I

未找到 spll 怎么设置.png

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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi jinsheng20,

The Phase-locked loop (PLL) is not available for the S32K11x product series. That is why you cannot configure it.

Figure 27-1. Clocking diagram.png

Best Regards,
Robin
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Robin_Shen
NXP TechSupport
NXP TechSupport

Hi jinsheng20,

The Phase-locked loop (PLL) is not available for the S32K11x product series. That is why you cannot configure it.

Figure 27-1. Clocking diagram.png

Best Regards,
Robin
-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
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1090097669
Contributor IV

Hi Robin,

according to Datasheert,the  and the current consumption it is 21mA,and following Code which the current consumption it is 4mA,it should be less than 1mA.
how to further reduce the current consumption by the controller?
 And also how to disable the clock monitors?
And if possible also let me know how to come to normal RUN mode through CAN
 
Please point out my configuration errors or missing areas
 
void power_cp_wakeup_set(void)/*E5*/
{
PINS_DRV_SetPinIntSel(GPIO_CP_WAKE_PORT,GPIO_CP_WAKE_PIN,PORT_INT_RISING_EDGE);
}
 
void init_NVIC(void)
{
 
power_cp_wakeup_set();
INT_SYS_ClearPending(PORTE_IRQn);
INT_SYS_SetPriority(PORTE_IRQn, 0);
 
// PORTE_interrupt
S32_NVIC-> ICPR [1] = (1 <<(63%32));
S32_NVIC-> ISER [1] = (1 <<(63%32));
S32_NVIC-> IP [63] = 0x10;
PORTE-> DFER |= (1 << 5);
}
 
void Power_RUN_to_STOP (void)
{
#if 0
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
S32_SCB->SCR |= S32_SCB_SCR_SLEEPDEEP_MASK;
/*select stop mode*/
SMC->PMCTRL = SMC_PMCTRL_STOPM(0b00);
SMC->STOPCTRL = SMC_STOPCTRL_STOPO(0b01);
if(SMC->PMSTAT == 0x01)
{
asm("WFI");
}
#else
/* Disable the JTAG port pins */
/* Disable Adc Pins */
 
PMC->REGSC |= PMC_REGSC_BIASEN(1); // [1] CLKBIASDIS = 1 In VLPS mode, the bias current for SIRC, FIRC, PLL is disabled
 
/* Disable the Fosc and Sosc from chip*/
SCG->FIRCCSR = SCG_FIRCCSR_FIRCEN(0);
while(SCG->FIRCCSR & (1 << 24));
SCG->SOSCCSR = SCG_SOSCCSR_SOSCEN(0);
 
S32_SCB->SCR |= S32_SCB_SCR_SLEEPDEEP_MASK|0x2; /* allow deep sleep mode0 */
SMC->PMPROT = SMC_PMPROT_AVLP(1); /* allow very low power mode*/
 
 
SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
 
if(SMC->PMSTAT == 0x01)
{
asm("WFI");
}
#endif
 
}
 
void power_set_mode(POWER_SYS_TYPE mod)
{
if(mod == POWER_SYS_SLEEP)
{

init_NVIC();
//power_can_wakeup_set();
Power_RUN_to_STOP();
}
}
Regards,

Katrinal
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