FlexCAN Clock Source for S32K142 EVB

[Gauri_n]

We are using FlexCAN0 for CAN communication with 500kbps baud rate.

CAN communication is not working when Clock source is configured as SYS_CLK. SYS_CLK is configured as 80MHz with prescaler as 10 to get Sclock as 8MHz

But with the same bit timing values and Clock source configured as SOSCDIV2 CAN communication is working fine. SOSCDIV2 is configured as 8MHz with prescaler as 1 to get Sclock as 8MHz

Is there any limitation on using SYS_CLK as clock source for FlexCAN0 in EVB?

[Gauri_n]

I could see your configuration is using PE clock source as Oscillator clock. CAN communication is working for us when we are using Oscillator clock which takes the external oscillator frequency of 8MHz from S32K142 EVB

We are facing issue when using System clock as 80MHz(for Normal Run mode as per S32K142 reference manual example and PE clock source as Peripheral Clock. Also in the first screen shot you have provided, configuration for SPLL_CLK is 80MHz and System clock as 8MHz. But in our case System clock is 80MHz

Could you please check and let me know if there is any issue with configuring PE clock source as Peripheral clock?

Note: For configuration for CAN Stack we are using EB Tresos tool for S32K14X

[Senlent]

Hi@Gauri_n

I think this should still be a problem of clock configuration.

my configuration: RUN Mode

Senlent_1-1626777471421.png

Senlent_2-1626777652981.png

It works fine, but  i just tested 'receive' only.

If the problem is still not resolved, I can help you check your code.

BR!

Jim.

[Gauri_n]

Hi,

I checked again with the same bit timing values and clock configuration as you had given. I could find the issue. The issue is CTRL1[CLKSRC] is not set as 1 even though the clock source is configured as peripheral clock.

As I had mentioned in the previous message we are using EB Tresos tool for CAN driver configurations. In code from EB Tresos, CTRL1[CLKSRC] is being set with configured clock source after reset of MCR[MDIS] register due to which MCR[NOTRDY] is also reset. This seems to be an issue in EB Tresos code.

I understand CTRL1[CLKSRC] should be set before reset of MCR[MDIS]. Could you please let me know if this understanding correct? Is there any other conditions to be considered for setting CTRL1[CLKSRC]?

Thank you for your support

[Senlent · Accepted solution]

Hi@Gauri_n

 Happy to see you solved the problem.

I found some content from the datasheet, and I think yours idea is correct. 

Senlent_1-1626850958802.png

I am not familiar with EB Tresos ,  so I may not be able to help you fix this bug.

If this post answers your question, please click the "Mark Correct" button. Thank you

Best Regards!

 Jim.

[Gauri_n]

Hi,

Thank you for the confirmation.

We will check this further with EB tresos team.

[Senlent]

Hi@Gauri_n

             I use your method to configure the clock module then IDE shows some errors.I think this question may be caused by your clock configuration error.

Senlent_0-1626159960174.png

Senlent_1-1626160281900.png

Below is my test and it works fine.

Senlent_2-1626161378224.png

Senlent_0-1626163867012.png

Senlent_1-1626163874795.png

Hope this answer can help you.

Best Regards!

Jim