DMA half major loop issue

[Ayaz]

Hi,
I’ve designed a setup where the DMA is triggered by a PIT every 25 µs to transfer data from one buffer to another. This happens 10 times per major loop, so the full major loop completes every 250 µs — which I can confirm using a logic analyzer.

PIT--> DMA ---> major loop Interrupts 

Now, I’m trying to configure the DMA to trigger an interrupt at half the major loop interval (i.e., every 125 µs). However, the interrupt still only fires every 250 µs, as if the half-major loop interrupt feature isn’t working.

To help investigate this, I’ve created an example project that you can look at. I’d appreciate your help in figuring out why the half-major loop interrupt isn’t triggering as expected.
Also, I have one more question:
What is the "End of Packet Signal" in the context of DMA, and how is it typically used?

[PetrS]

Hi,

if you have period trigger and enable DMA half major interrupt only, the fist trigger happens after half interval (125us) but subsequent interrupts will be triggered again at 250us rate. Enable both half major and major interrupts and you get interrupt each 125us.

The "End of Packet Signal" feature should be disabled, I think. Some discussion was done in 
https://community.nxp.com/t5/S32-Design-Studio/Possible-bug-in-DMA-RTD-driver/td-p/1701972

BR, Petr