Clock Division error in S32K1xx Reference Manual

[AergoXenn]

Hello,

On sections 28.3.9, 28.3.12, 28.3.15 and 28.3.18 I have found an inconsistency regarding the contents of the S32K1XX.h library provided through S32DesignStudio.

The sections refer to the SOSCDIV, SIRCDIV, FIRCDIV and SPLLDIV register maps. The error is consistent in all of them: the definitions are missing for the xxxxDIV1 bit fields, although they are present in both the S32k libraries and S32DS IDE debug/trace register definitions.

This caused issues when configuring the device (S32K148) as we had to experiment with the configurations of the divisions until we found this error.

As you can see, the bit field from 3:0 does not have a name, nor a definition/explanation of its configuration. We had assumed this was a reserved space and so it was left unused, however the IDE and libraries showed the opposite. 

There is also an inconsistency between the cookbook and reference manuals, where the EREFS bitfield in the SOSCCFG register is defined to be:

0 - External reference clock selected

1 - Internal crystal oscillator of OSC selected

Where as the opposite is true for the cookbook. I have confirmed the RM is incorrect, given that the processor does not trigger SOSCVLD flag when configured according to reference manual, but works when configured following the Cookbook's instruction.

I hope this can be helpful for others. Greetings!

[AergoXenn]

Hello Robin,

Thanks for replying.

I am currently developing on the S32K148EVB-Q176 Evaluation Board.

SOSCVLD flag is asserted by the µC and every other clock configuration works when following cookbok. It seemed to me like the definitions were inverted on the RM, since the EVB used an external crystal and not FIRC/SIRC as reference. I now understand it refers to "external clock" as a clock signal from an external oscillator, not a crystal on EXTAL and XTAL pins using the internal oscillator of the chip.

Thank you for your help, this has cleared my misunderstanding.

Best Regards,

AK.

[Robin_Shen · Accepted solution]

Hi AergoXenn,

Thank you for the report!
I have reported the missing of SCG_SOSCDIV[SOSCDIV1] in S32K-RM (Rev. 14, 09 2021). You can refer the description of S32K-RM (Rev. 13)

About the SCG_SOSCCFG[EREFS], please tell me your hardware:
external reference clock at EXTAL pin(EREFS=0)
or
crystal at EXTAL and XTAL pin(EREFS=1)
SCG_SOSCCSR[SOSCVLD] will be set after 4096 xtal counts

8MHz crystal is used in AN5413, so the SCG_SOSCCFG[EREFS]=1 and need to wait System OSC Valid SCG_SOSCCSR[SOSCVLD].

Best Regards,
Robin
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