CSEc secure boot and reset signal

[snaku_lee]

Hi,

I have a question about the CSEc secure boot with sequential boot mode.

I want to measure the secure boot time from reset pin release to high, but I find there is no different while secure boot with different BOOT_SIZE?

So I guess when the secure boot is start to boot (i.e., the CSEc is computing the CMAC), the CPU core stay in reset state, and the reset pin also hold in low state, until CMAC compuing finish, am I right ?

Regards,

Snaku

[danielmartynek · Accepted solution]

Hi Snaku,

You can find some execution time specs in AN5401.

You are right, the reset_b pin is driven low as long as the core is in the reset state.

You can measure the time between a rising edge on the VDD power supply (after POR) and the rising edge on reset_b.

Regards,

Daniel

[snaku_lee]

Hi Daniel,

I got it, thanks for your support.

Snaku