S32K144 MPU Region0 Question

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S32K144 MPU Region0 Question

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kmh48301
Contributor IV

Hello.

 

I have been studying SDK example project, 'mpu_memory_protection'.

 

I don't understand the 'memProtect1_UserConfig0' Array.

 

I think I can allocate each region by changing each value in the array

(startAddr, endAddr, masterAccRight)

 

But It seems Region0 is default. So it is not supposed to be changed by user.

Is it correct?

=====================================================================

I changed the 'memProtect1_AccessRightConfig0' Array, like below.

kmh48301_0-1630386080215.png

I ran it. And he MPU didn't work...

Why??

 

Then,

If I want to protect some region from DEBUGGER, do i have to change the region0 access right like below?

 

kmh48301_1-1630386234088.png

 

I couldn't find any contents about this in RM.

 

Please help me.

 

Thanks

Best regards

Phillip

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Phillip,

I still don't know what you mean.

memProtect1_AccessRightConfig0 cover the whole memory and does not allow the core to access it. Therefore, there is memProtect1_AccessRightConfig1 that gives the core access to the PFlash (up to 0x0007FEFF) so that it can execute and read the code/data.

0x0007FF00 - 0x0007FF1F of PFlash is covered by memProtect1_AccessRightConfig2 & memProtect1_AccessRightConfig3. When memProtect1_AccessRightConfig3 gets disabled, the CORE cannot read that region, because memProtect1_AccessRightConfig2 allows writing and executing only.

The rest of the memory map is covered by memProtect1_AccessRightConfig1 again but in Region 4.

 

If this does not answer your questions, please elaborate.

Thank you,

BR, Daniel

 

 

 

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Philip,

Descriptor 0 has been discussed many times here on the community, please refer to these threads for example:

https://community.nxp.com/t5/S32-Design-Studio/S32K144-s-MPU-issue/m-p/1015041/highlight/true

https://community.nxp.com/t5/S32K/MPU-Region0/m-p/930923

 

Regarding the change you made,

the core access is already enabled in region 1

danielmartynek_0-1630400474577.png

What result do you expect from the modification?

 

Thank you,

BR, Daniel

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kmh48301
Contributor IV

Hi, Daniel

 

Thanks for replying.

 

 

I have read links you gave.

But, I couldn't solve my question.

 

My question is about SDK example project, 'mpu_memory_protection' and Region0 access right.

 

In the example project,

MPU_DRV_Init() : Set the MPU, But no activate.

and its main parameter is 'memProtect1_UserConfig0'.

 

In 'memProtect1_UserConfig0',

==================================================

kmh48301_0-1630452988889.png

kmh48301_1-1630453079024.png

====================================================

kmh48301_2-1630453127526.pngkmh48301_3-1630453158633.png

==================================================

Region2 is Region2 but it is also region0.

<<So, how can i know that which AccessRightConfig will be applied? (AccessRightConfig 0 or 2)>>

<<>> : is my main question.

 

So I tested changing memProtect1_AccessRightConfig0.

and the mpu didn't work. [when i pushed the button, HardFault_Handler was not called.]

The result means changing memProtect1_AccessRightConfig0 affect region2.

 

Thanks

Best regards

Phillip

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danielmartynek
NXP TechSupport
NXP TechSupport

Hi Phillip,

I still don't know what you mean.

memProtect1_AccessRightConfig0 cover the whole memory and does not allow the core to access it. Therefore, there is memProtect1_AccessRightConfig1 that gives the core access to the PFlash (up to 0x0007FEFF) so that it can execute and read the code/data.

0x0007FF00 - 0x0007FF1F of PFlash is covered by memProtect1_AccessRightConfig2 & memProtect1_AccessRightConfig3. When memProtect1_AccessRightConfig3 gets disabled, the CORE cannot read that region, because memProtect1_AccessRightConfig2 allows writing and executing only.

The rest of the memory map is covered by memProtect1_AccessRightConfig1 again but in Region 4.

 

If this does not answer your questions, please elaborate.

Thank you,

BR, Daniel

 

 

 

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