About FLEXIO Timer Operation Question

[584914019]

52.4.3.6 Timer Disable and Stop Bit

Timer output will clear. Shifters that are controlled by this timer do not see this as a
falling edge on the timer shift clock, but can generate a shift event if the timer shift
clock would otherwise generate one

This description is incomprehensible, can you elaborate on it

[victorjimenez]

Hello, 

To provide you better support, could you please specify where exactly did you see that description? 

Regards, 

Victor 

[584914019]

S32K-RM-2019 52.4.3.6 chapter

[victorjimenez]

Hello, 

You have an old version of the S32K reference manual, you can download the newest version available from the following link.

Now regarding the statement. When the condition configured by timer disable (TIMDIS) is detected, the output of the timer will be cleared, it doesn't matter what is the value of the timer, once this condition is detected this output will be cleared automatically. Clearing the output of the timer won't affect the shifters controlled by this timer, this means that the values won't be shifted when this condition occurs unless you generate a shift event with the timer shift clock. 

Regards, 

Victor