********************************************************************************************** * Detailed Description: * CMU_FM minimum reference count requirement: * RCCR[REF_CNT]_MIN = CEILING(MAX(3 * (f_reference_clock / f_bus_clock), * 8 + 5 * (f_reference_clock / f_monitored_clock))) * where: * f_reference_clock = FXOSC clock frequency * f_bus_clock = AIPS_SLOW_CLK frequency (40 MHz) * f_monitored_clock = metered clock frequency * * CMU_1 * ----- * FIRC clock frequency (fmonitored) = 48 MHz * FXOSC clock frequency (fref) = 16 MHz * * 3 * (fref / fbus) = 3 * (16 / 40) = 1.2 * 8 + 5 * (fref / fmonitored) = 8 + 5 * (16 / 48) = 9.667 * RCCR[REF_CNT]_MIN = CEILING(MAX(1.2, 9.667)) = 10 * The first term would dominate only at f_bus_clock < 4.96 MHz, for example. * * CMU_2 * ----- * SIRC clock frequency fmonitored = 32 kHz * FXOSC clock frequency (fref) = 16 MHz * * 3 * (fref / fbus)= 3 * (16 MHz / 40 MHz) = 1.2 * 8 + 5 * (fref / fmonitored) = 8 + 5 * (16 MHz / 32 kHz) = 2508 * RCCR[REF_CNT]_MIN = CEILING(MAX(1.2, 2508)) = 2508 * * * SR_FMTO (Frequency Meter Time Out): * --------------------------------------------------------------------- * FMTO could theoretically be triggered by configuring RCCR[REF_CNT] * to a value lower than the minimum number of reference clock cycles * required to observe one full monitored clock period. * This however cannot be guaranteed by NXP as the value is lower then RCCR_MIN. * NXP guarantees the MCU functionality only if RCCR > RCCR_MIN * When SR_FMTO is set, the SR_FMC is never set, and therefore the CMU_FM interrupt is never called. * * CMU_FM_1: * RCCR[REF_CNT] < f_FIRC / f_FXOSC < (48 MHz / 16 MHz) < 3 * CMU_FM_2: * RCCR[REF_CNT] < T_SIRC / T_FXOSC < 31.25 µs / 62.5 ns < 500 * * * POR_WDG: * --------------------------------------------------------------------- * In case CMU_FM_1 ISR is not executed within POR_WDG timeout, the MCU is reset by the POR_WDG. * Read DCMROPP1-4 * To inject this reset, select CMUFM_1_POR_WDG = 1 and CMUFM_1. * ------------------------------------------------------------------------------------- * MCU: S32K344 * FX_OSC: 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: Lauterbach Trace32 * Target: Internal_FLASH **********************************************************************************************

**************************************************************************************** * Detailed Description: * * UART <-> Ethernet gateway demo for S32K344EVB-T172. * * UART messages are encapsulated into raw Ethernet frames * and transmitted over the Ethernet link. Received Ethernet * frames are decapsulated and forwarded to the UART terminal. * * Key Functionality: * - UART TX/RX interrupt driven communication. * - GMAC TX confirmation and RX indication interrupt processing. * - Four-deep message queue for UART/Ethernet decoupling. * - Runtime MAC address configuration. * - TJA1103 loopback, MASTER and SLAVE operation. * - Raw Ethernet frame transport (EtherType 0x88B5). * - RTD MCAL/HLD implementation (EthIf, Eth_43_GMAC, CDD_UART). * * Runtime status information including node configuration, * MAC addresses and link status is displayed on the UART terminal. * * Test Configurations: * * Single board: * GATEWAY_MODE_NODE_1_LOOPBACK * * Two-board setup: * Board 1 : GATEWAY_MODE_NODE_1_MASTER * Board 2 : GATEWAY_MODE_NODE_2_SLAVE * * Boards are connected using a 100BASE-T1 cable. * * Notes: * - EthIf.c contains custom gateway callback implementation. * - During S32 Configuration Tool code generation select "Keep Existing" for EthIf.c. * - Do not overwrite EthIf.c. * - On PC terminal enable local echo * * -------------------------------------------------------------------------------------- * Test HW: S32K3x4EVB-T172 Rev B * MCU: S32K344_172HDQFP * IDE: S32DS 3.6.8 * RTD release: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: Lauterbach, P&E Micro * Target: Internal_FLASH * Serial: 115200, 8N1 *****************************************************************************************   Terminal prints between two S32K344EVB-T172 boards PetrS_0-1789458752395.png In case of single board in PHY loopback PetrS_1-1789458817163.png    

**************************************************************************************************** * Detailed Description: * * CM7_0 Safety Core (Lockstep): * * Runs as Domain 0 on the CM7_0+CM7_1 lockstep core pair of the S32K358. * Acts as the system master: performs full initialization of clocks, XRDC * domain assignment and memory region protection (Rm_Init), Port, Platform, * and releases CM7_2 from reset via Mcu_SetMode(McuModeSettingConf_1). * * XRDC memory layout configured by Rm_Init: * - 0x20480000 (SHARED_VARIABLE): Domain 0 RW, Domain 1 RW — Sema42 Ch 0 protected * - 0x20480010 (SHARED_FAULT_FLAG): Domain 0 RW, Domain 1 RW — Sema42 Ch 1 protected * - 0x20490000 (CM_0_OWNED_VARIABLE):Domain 0 RW, Domain 1 NO ACCESS — exclusive to CM7_0 * * Two Sema42 channels are used: * - Channel 0: guards the shared counter at 0x20480000 (competed with CM7_2) * - Channel 1: guards the fault flag at 0x20480010 (CM7_0 monitors CM7_2 violations) * * Main loop (continuous): * - Writes to the owned SRAM region (0x20490000) directly, without a semaphore — * XRDC guarantees exclusive Domain 0 access. Blinks BLUE LED on each write. * - Acquires Sema42 Ch 0, increments the shared counter at 0x20480000, * releases Ch 0. Competes with CM7_2 for the gate — mutual exclusion * is visible as either core stalls while the other holds the semaphore. * * XRDC_ISR_Handler (triggered by XRDC interrupt when CM7_2 violates 0x20490000): * - Spins on Sema42 Ch 1 until CM7_2's HardFault handler sets the shared * fault flag at 0x20480010, confirming CM7_2 has handled the violation. * - Acquires Ch 1 and clears the fault flag, signaling CM7_2 to resume * its main loop cycle. * - Together with CM7_2's HardFault handler, this implements a lightweight * cross-core fault notification and recovery handshake. * * CM7_2 Application Core * * Runs as Domain 1 on the independent CM7_2 core of the S32K358. * Only Sema42 is initialized here — XRDC and full RM initialization * are handled exclusively by CM7_0 (Domain 0, lockstep) before this core is released from reset. * * Two Sema42 channels are used: * - Channel 0: guards the shared counter at 0x20480000 (competed with CM7_0) * - Channel 1: guards the fault flag at 0x20480010 (CM7_2 signals CM7_0) * * Main loop (repeating cycle of 10 iterations, i = 0..8 + violation): * - Before each iteration, CM7_2 reads the shared fault flag via Ch 0 * and spins until CM7_0 clears it (fault recovery synchronization). * - Iterations 0..8 (9x): acquires Ch 0, increments the shared counter, * releases Ch 0, blinks GREEN LED to indicate successful access. * - Iteration 9: deliberately writes 0xDEAD to CM7_0's owned SRAM region * (0x20490000), which has no XRDC access for Domain 1. * This triggers a HardFault on CM7_2. After fault handling, variable i is reset * to 0 and the cycle repeats indefinitely. * * HardFault handler (triggered by XRDC violation on iteration 9): * - Lights RED LED immediately. * - Calls Rm_XrdcGetDomainIDErrorStatus() to read and decode the XRDC * error registers (domain, faulting address, access type, attribute). * Error registers are cleared automatically inside this API call. * - Acquires Sema42 Ch 1 and sets the shared fault flag at 0x20480010 * to notify CM7_0 that a violation was detected. ------------------------------------------------------------------------------------------------ * MCU: S32K358 * FXOSC 16MHz * RTD: S32K3_RTD_7_0_1_D2602_ASR_REL_4_9_REV_0000_20260206 * Debugger: PE Micro Multilink * Target: Internal_FLASH ****************************************************************************************************