Hi, NXP
We use bootloader to boot M core + A core, M core configured with llce_lin output;
S32g u-boot jumps to kernel, llce_lin output is broken, query the specific code and found;
u-boot code: bootm.c->announce_and_cleanup()-> cleanup_before_linux(void)->board_cleanup_before_linux();->scmi_reset_agent();
we found that because of the call to the scmi_reset_agent function leads to, the M core configure llce_lin to stop sending;
due to scmi ( System Control and Management Interface The system control and management interface (SCMI) is a lower level function in u-boot and kernel, controlling clock, power, io, reset, etc., which involves the underlying control logic of s32g;
How to modify or configure to solve the problem of initialization of A-core which leads to the stoppage of llce_lin?
Best regards,
The transition from U-Boot to the Linux kernel can indeed affect the output of peripherals, including those related to LLCE-LIN (Low Latency Communication Engine - Local Interconnect Network), especially in complex embedded systems like the NXP S32G. This is primarily due to the different ways U-Boot and the monkey type Linux kernel manage and initialize hardware resources. We use bootloader to boot M core + A core, M core configured with llce_lin output; S32g u-boot jumps to kernel, llce_lin output is broken, query ...However, they serve different purposes and are managed quite differently. ->U-boot device tree is used to configure and initialize the hardware components needed during the boot process, while the Linux kernel used the device tree to describe the hardware configuration once the kernel is booted.
hi,nxp
I am continuing to trace the code in u-boot and found the following:
call chain: scmi_reset_agent(void) ->
devm_scmi_process_msg(dev, &scmi_msg) ->
scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg)->
arm_smccc_smc(chan->func_id, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &res);->
SMCCC smc
The final call to the assembly is made, and I don't know the relevant details, so what does this part of the code do? How does it affect the M core operation and how can I skip this part of the code execution.
BR.
Hello, @Masson
Thanks for the reply.
From my understanding, the U-boot will not set the clock, the tfa will set it during the boot.
For current issue, would you mind testing it by commenting out the scmi_reset_agent from the source, to check if there is still issue existed in your test?
BR
Chenyin
Hi,chenyin
I now have some questions about the clock in the S32G, basically similar to the questions in the picture;
1. won't tf-a exit after tf-a initializes the clock?
2. how does u-boot and kernel initialize or use the clock,Need to communicate with tf-a?
3. can you explain in detail how clk is used in tf-a, u-boot and kernel?
BR.
Hi,chenyin
Thanks for the reply
I tested the commented scmi_reset_agent function and confirmed that the llce_lin output is normal during the u-boot->kernel jump.
However, I found that there are anomalies after kernel boot, such as eth0 ping can not be reached, because I am not sure if there are other problems, so I did not follow this line of investigation;
Do you suggest me to do this kind of investigation?
BR.
Hello, @Masson
Thanks for your reply.
Commenting out the corresponding line is only a kind of test, it is not suggested way to fix the issue, since it may impact several parts, which may cause issues like you had found.
I think further analysis and test are needed, for more convenient discussion and resource sharing, let me help to create a support case to continue the support, I will directly reply you there via mails.
Sorry for your inconvenience.
BR
Chenyin
Hi,chenyin
Please advise a question, we are now booting the flow as follows
bootloader(M7)->tf-a(A53)->u-boot(A53)->kernel(A53)
We have configured the uart clock in the bootloader, the uart clock is not configured in the tf-a, and no modification is made in the u-boot;
Will the uart module and clock be reconfigured in u-boot?
BR.
Hello, @Masson
Thanks for your reply.
Since only ddr, xbar_2x clocks are kept in your tf-a, u-boot, do you mean that the clock for UART and Peripheral PLL3 are also disabled and set in bootloader instead of in TF-A?(the TFA/uboot only inherit the clock settings from bootloader to drive the UART using in TFA/uboot?)
BR
Chenyin
Hello, @Masson
Thanks for your post.
1. May I know if the LIN clock is configured in your bootloader or the LIN application running on the M7 core?
2. Which version BSP is used in your test setup? any modifications for the clock settings? would you mind sharing the clock dump from your u-boot?
BR
Chenyin
Hi,chenyi
The clk dump in u-boot is as follows:
=> clk dump
Rate Usecnt Name
------------------------------------------
40000000 0 |-- fxosc@40050000
51000000 0 |-- firc
32000 0 |-- sirc
20000000 0 |-- ftm0_ext
20000000 0 |-- ftm1_ext
125000000 0 |-- gmac0_ext_rx
125000000 0 |-- gmac0_ext_tx
50000000 0 |-- gmac0_rmii_ref
200000000 0 |-- gmac0_ext_ts
100000000 0 |-- serdes_100_ext
125000000 0 |-- serdes_125_ext
125000000 0 |-- serdes0_lane0_ext_cdr
125000000 0 |-- serdes0_lane0_ext_tx
125000000 0 |-- serdes0_lane1_ext_cdr
125000000 0 |-- serdes0_lane1_ext_tx
125000000 0 |-- serdes1_lane0_ext_cdr
125000000 0 |-- serdes1_lane0_ext_tx
125000000 0 |-- serdes1_lane1_ext_cdr
125000000 0 |-- serdes1_lane1_ext_tx
1 0 |-- pfe_mac0_rmii
1 0 |-- pfe_mac1_rmii
1 0 |-- pfe_mac2_rmii
1000000000 0 |-- a53
400000000 1 |-- serdes_axi
51000000 1 |-- serdes_aux
133333333 1 |-- serdes_apb
100000000 1 |-- serdes_ref
80000000 0 |-- ftm0_sys
0 0 |-- ftm0_ext
80000000 0 |-- ftm1_sys
0 0 |-- ftm1_ext
133333333 0 |-- flexcan_reg
133333333 0 |-- flexcan_sys
40000000 0 |-- flexcan_can
200000000 0 |-- flexcan_ts
62500000 0 |-- linflex_xbar
125000000 1 |-- linflex_lin
0 0 |-- gmac0_ts
125000000 0 |-- gmac0_rx_sgmii
125000000 0 |-- gmac0_tx_sgmii
125000000 1 |-- gmac0_rx_rgmii
125000000 1 |-- gmac0_tx_rgmii
0 0 |-- gmac0_rx_rmii
0 0 |-- gmac0_tx_rmii
0 0 |-- gmac0_rx_mii
0 0 |-- gmac0_tx_mii
400000000 1 |-- gmac0_axi
0 0 |-- spi_reg
0 0 |-- spi_module
133333333 0 |-- qspi_reg
133333333 0 |-- qspi_ahb
266666666 0 |-- qspi_flash2x
133333333 0 |-- qspi_flash1x
400000000 0 |-- usdhc_ahb
133333333 0 |-- usdhc_module
400000000 1 |-- usdhc_core
32000 0 |-- usdhc_mod32k
133333333 0 |-- ddr_reg
800000000 0 |-- ddr_pll_ref
800000000 0 |-- ddr_axi
400000000 0 |-- sram_axi
133333333 0 |-- sram_reg
133333333 0 |-- i2c_reg
133333333 0 |-- i2c_module
66666666 0 |-- siul2_reg
51000000 0 |-- siul2_filter
133333333 0 |-- crc_reg
133333333 0 |-- crc_module
100000000 0 |-- eim0_reg
100000000 0 |-- eim0_module
66666666 0 |-- eim123_reg
66666666 0 |-- eim123_module
66666666 0 |-- eim_reg
66666666 0 |-- eim_module
66666666 0 |-- fccu_module
51000000 0 |-- fccu_safe
66666666 0 |-- rtc_reg
32000 0 |-- rtc_sirc
51000000 0 |-- rtc_firc
133333333 0 |-- swt_module
51000000 0 |-- swt_counter
133333333 0 |-- stm_module
133333333 0 |-- stm_reg
133333333 0 |-- pit_module
133333333 0 |-- pit_reg
400000000 0 |-- edma_module
400000000 0 |-- edma_ahb
80000000 1 |-- sar_adc_bus
66666666 0 |-- cmu_module
66666666 0 |-- cmu_reg
133333333 0 |-- tmu_module
133333333 0 |-- tmu_reg
133333333 0 |-- flexray_reg
0 0 |-- flexray_pe
66666666 0 |-- wkpu_module
66666666 0 |-- wkpu_reg
66666666 0 |-- src_module
66666666 0 |-- src_reg
66666666 0 |-- src_top_module
66666666 0 |-- src_top_reg
133333333 0 |-- ctu_module
80000000 0 |-- ctu_ctu
200000000 0 |-- dbg_sys4
400000000 0 |-- dbg_sys2
400000000 0 |-- m7
133333333 0 |-- dmamux_module
133333333 0 |-- dmamux_reg
500000000 0 |-- gic_module
133333333 0 |-- mscm_module
133333333 0 |-- mscm_reg
133333333 0 |-- sema42_module
133333333 0 |-- sema42_reg
66666666 0 |-- xrdc_module
66666666 0 |-- xrdc_reg
0 0 |-- clkout0
0 0 |-- clkout1
100000000 0 |-- usb_mem
32000 0 |-- usb_low
0 0 |-- pfe0_rx_sgmii
0 0 |-- pfe0_tx_sgmii
0 0 |-- pfe0_rx_rgmii
0 0 |-- pfe0_tx_rgmii
0 0 |-- pfe0_rx_rmii
0 0 |-- pfe0_tx_rmii
0 0 |-- pfe0_rx_mii
0 0 |-- pfe0_tx_mii
0 0 |-- pfe1_rx_sgmii
0 0 |-- pfe1_tx_sgmii
0 0 |-- pfe1_rx_rgmii
0 0 |-- pfe1_tx_rgmii
0 0 |-- pfe1_rx_rmii
0 0 |-- pfe1_tx_rmii
0 0 |-- pfe1_rx_mii
0 0 |-- pfe1_tx_mii
0 0 |-- pfe2_rx_sgmii
0 0 |-- pfe2_tx_sgmii
0 0 |-- pfe2_rx_rgmii
0 0 |-- pfe2_tx_rgmii
0 0 |-- pfe2_rx_rmii
0 0 |-- pfe2_tx_rmii
0 0 |-- pfe2_rx_mii
0 0 |-- pfe2_tx_mii
300000000 0 |-- pfe_axi
300000000 0 |-- pfe_apb
600000000 0 |-- pfe_pe
0 0 |-- pfe_ts
40000000 0 |-- llce_can_pe
200000000 0 |-- llce_sys
80000000 0 `-- llce_per
1000000000 0 |-- a53
400000000 1 |-- serdes_axi
51000000 1 |-- serdes_aux
133333333 1 |-- serdes_apb
100000000 1 |-- serdes_ref
80000000 0 |-- ftm0_sys
0 0 |-- ftm0_ext
80000000 0 |-- ftm1_sys
0 0 |-- ftm1_ext
133333333 0 |-- flexcan_reg
133333333 0 |-- flexcan_sys
40000000 0 |-- flexcan_can
200000000 0 |-- flexcan_ts
62500000 0 |-- linflex_xbar
125000000 1 |-- linflex_lin
0 0 |-- gmac0_ts
125000000 0 |-- gmac0_rx_sgmii
125000000 0 |-- gmac0_tx_sgmii
125000000 1 |-- gmac0_rx_rgmii
125000000 1 |-- gmac0_tx_rgmii
0 0 |-- gmac0_rx_rmii
0 0 |-- gmac0_tx_rmii
0 0 |-- gmac0_rx_mii
0 0 |-- gmac0_tx_mii
400000000 1 |-- gmac0_axi
0 0 |-- spi_reg
0 0 |-- spi_module
133333333 0 |-- qspi_reg
133333333 0 |-- qspi_ahb
266666666 0 |-- qspi_flash2x
133333333 0 |-- qspi_flash1x
400000000 0 |-- usdhc_ahb
133333333 0 |-- usdhc_module
400000000 1 |-- usdhc_core
32000 0 |-- usdhc_mod32k
133333333 0 |-- ddr_reg
800000000 0 |-- ddr_pll_ref
800000000 0 |-- ddr_axi
400000000 0 |-- sram_axi
133333333 0 |-- sram_reg
133333333 0 |-- i2c_reg
133333333 0 |-- i2c_module
66666666 0 |-- siul2_reg
51000000 0 |-- siul2_filter
133333333 0 |-- crc_reg
133333333 0 |-- crc_module
100000000 0 |-- eim0_reg
100000000 0 |-- eim0_module
66666666 0 |-- eim123_reg
66666666 0 |-- eim123_module
66666666 0 |-- eim_reg
66666666 0 |-- eim_module
66666666 0 |-- fccu_module
51000000 0 |-- fccu_safe
66666666 0 |-- rtc_reg
32000 0 |-- rtc_sirc
51000000 0 |-- rtc_firc
133333333 0 |-- swt_module
51000000 0 |-- swt_counter
133333333 0 |-- stm_module
133333333 0 |-- stm_reg
133333333 0 |-- pit_module
133333333 0 |-- pit_reg
400000000 0 |-- edma_module
400000000 0 |-- edma_ahb
80000000 1 |-- sar_adc_bus
66666666 0 |-- cmu_module
66666666 0 |-- cmu_reg
133333333 0 |-- tmu_module
133333333 0 |-- tmu_reg
133333333 0 |-- flexray_reg
0 0 |-- flexray_pe
66666666 0 |-- wkpu_module
66666666 0 |-- wkpu_reg
66666666 0 |-- src_module
66666666 0 |-- src_reg
66666666 0 |-- src_top_module
66666666 0 |-- src_top_reg
133333333 0 |-- ctu_module
80000000 0 |-- ctu_ctu
200000000 0 |-- dbg_sys4
400000000 0 |-- dbg_sys2
400000000 0 |-- m7
133333333 0 |-- dmamux_module
133333333 0 |-- dmamux_reg
500000000 0 |-- gic_module
133333333 0 |-- mscm_module
133333333 0 |-- mscm_reg
133333333 0 |-- sema42_module
133333333 0 |-- sema42_reg
66666666 0 |-- xrdc_module
66666666 0 |-- xrdc_reg
0 0 |-- clkout0
0 0 |-- clkout1
100000000 0 |-- usb_mem
32000 0 |-- usb_low
0 0 |-- pfe0_rx_sgmii
0 0 |-- pfe0_tx_sgmii
0 0 |-- pfe0_rx_rgmii
0 0 |-- pfe0_tx_rgmii
0 0 |-- pfe0_rx_rmii
0 0 |-- pfe0_tx_rmii
0 0 |-- pfe0_rx_mii
0 0 |-- pfe0_tx_mii
0 0 |-- pfe1_rx_sgmii
0 0 |-- pfe1_tx_sgmii
0 0 |-- pfe1_rx_rgmii
0 0 |-- pfe1_tx_rgmii
0 0 |-- pfe1_rx_rmii
0 0 |-- pfe1_tx_rmii
0 0 |-- pfe1_rx_mii
0 0 |-- pfe1_tx_mii
0 0 |-- pfe2_rx_sgmii
0 0 |-- pfe2_tx_sgmii
0 0 |-- pfe2_rx_rgmii
0 0 |-- pfe2_tx_rgmii
0 0 |-- pfe2_rx_rmii
0 0 |-- pfe2_tx_rmii
0 0 |-- pfe2_rx_mii
0 0 |-- pfe2_tx_mii
300000000 0 |-- pfe_axi
300000000 0 |-- pfe_apb
600000000 0 |-- pfe_pe
0 0 |-- pfe_ts
40000000 0 |-- llce_can_pe
200000000 0 |-- llce_sys
80000000 0 |-- llce_per
Hi,chenyin
1. The Lin clock is configured in the bootloader;
2. we use bsp42, only ddr, xbar_2x clocks are kept in tf-a, u-boot, all other configurations are switched off, relying on the bootloader configuration;
BR.