Dear All,
I am using a custom s32g2 based hardware platform in which PFE2 is designed to work as "sgmii" using Serdes0 XPCS_1 channel 0
There is a PHY "TJA1104B" used in design
The pin details of MDC/MDIO is as mentioned in the the Schematic section attached.
The dts settings are:
---------------------
&pfe_mdio2 {
status = "okay";
/* TJA1104B */
pfe_mdio_b_phy2: ethernet-phy@2 {
reg = <0x3>;
};
};
&pfe_netif2 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&pfe_mdio_b_phy2>;
managed = "in-band-status";
};
pfe2mdioa_pins: pfe2mdioa_pins {
pfe2mdioa_grp0 {
pinmux = <S32CC_PINMUX(82, FUNC2)>;
//pinmux = <S32CC_PINMUX(80, FUNC1)>;
output-enable;
slew-rate = <S32CC_FAST_SLEW_166MHZ>;
};
pfe2mdioa_grp1 {
pinmux = <S32CC_PINMUX(79, FUNC2)>;
//pinmux = <S32CC_PINMUX(81, FUNC2)>;
output-enable;
input-enable;
slew-rate = <S32CC_FAST_SLEW_166MHZ>;
};
pfe2mdioa_grp2 {
pinmux = <S32CC_PINMUX(877, FUNC3)>;
//pinmux = <S32CC_PINMUX(877, FUNC2)>;
};
};
***********************************************************************
The problem is correct mux setting which is commented above does not work (Pin 80,81), but the which is UN-commented as above works (Pin 82,79)
This is very strange.
Can you suggest as how this is possible ?
Hello, @khan_misbah
Thanks for your post.
1. Per your description, if connecting the PHY to the S32G2 like the following:
Then setting the corresponding dts(79, 82), the PFE2 could work correctly, is it right?
2. If reworking the board, connect the PHY to S32G2 like the following:(no any other modification on the schematic?)
With only corresponding dts settings modification(80, 81), the PFE2 could not work as expected?
3. Would you mind also sharing the part number of the S32G2 used?
Thanks
BR
Chenyin
