I'm using three SGMII interfaces with the NXP PFEng driver in Linux. I can get two of them to load and operate (PFE1 + PFE2) but the third one (PFE0) is not being recognized by the driver.
It is saying "HIF0 not configured, skipped" but it is bound to PFE0 and configured the same as the rest from as far as I can tell.
Here is the device tree,
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2022-2023 NXP
*
*/
#include <dt-bindings/clock/s32g-scmi-clock.h>
#include <dt-bindings/reset/s32g-scmi-reset.h>
#include <dt-bindings/net/s32g-pfe.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83869.h>
/ {
aliases {
ethernet0 = &pfe_netif0;
ethernet1 = &pfe_netif1;
ethernet2 = &pfe_netif2;
};
soc {
pfe: pfe@46000000 {
compatible = "nxp,s32g-pfe";
reg = <0x0 0x46000000 0x0 0x1000000>,
<0x0 0x4007ca00 0x0 0x100>;
reg-names = "pfe-cbus", "s32g-main-gpr";
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "hif0", "hif1", "hif2",
"bmu", "upegpt", "safety";
resets = <&reset S32CC_SCMI_RST_PART2>;
reset-names = "pfe_part";
clocks = <&clks S32G_SCMI_CLK_PFE_AXI>,
<&clks S32G_SCMI_CLK_PFE_PE>,
<&clks S32G_SCMI_CLK_PFE_TS>;
clock-names = "pfe_sys", "pfe_pe", "pfe_ts";
nvmem-cells = <&pfe_emacs_intf_sel>, <&pfe_coh_en>,
<&pfe_pwr_ctrl>, <&pfe_genctrl3>;
nvmem-cell-names = "pfe_emacs_intf_sel", "pfe_coh_en",
"pfe_pwr_ctrl", "pfe_genctrl3";
// serdes, phy type, instance, lane
phys = <&serdes1 PHY_TYPE_XPCS 0 0>, // pfe0 connected to sgmii1, lane 0
<&serdes1 PHY_TYPE_XPCS 1 1>, // pfe1 connected to sgmii1, lane 1
<&serdes0 PHY_TYPE_XPCS 1 1>; // pfe2 connected to sgmii0, lane 1
phy-names = "emac0_xpcs", "emac1_xpcs", "emac2_xpcs";
dma-coherent;
memory-region = <&pfe_reserved_bmu2>, <&pfe_reserved_rt>,
<&pfe_reserved>, <&pfe_reserved_bdr>;
memory-region-names = "pfe-bmu2-pool", "pfe-rt-pool",
"pfe-shared-pool", "pfe-bdr-pool";
nxp,fw-class-name = "s32g_pfe_class.fw";
nxp,fw-util-name = "s32g_pfe_util.fw";
nxp,pfeng-ihc-channel = <PFE_HIF_CHANNEL_0>;
status = "okay";
/* MDIO on PFE0 */
pfe_mdio0: mdio@0 {
compatible = "nxp,s32g-pfe-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "okay";
pfe_mdiob_phy0: ethernet-phy@0 {
reg = <0>;
ti,op-mode = <DP83869_SGMII_COPPER_ETHERNET>;
};
};
/* MDIO on PFE1 */
pfe_mdio1: mdio@1 {
compatible = "nxp,s32g-pfe-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "okay";
pfe_mdiob_phy1: ethernet-phy@0 {
reg = <0>;
ti,op-mode = <DP83869_SGMII_COPPER_ETHERNET>;
};
};
/* MDIO on PFE2 */
pfe_mdio2: mdio@2 {
compatible = "nxp,s32g-pfe-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "okay";
pfe_mdiob_phy2: ethernet-phy@0 {
reg = <0>;
ti,op-mode = <DP83869_SGMII_COPPER_ETHERNET>;
};
};
/* Network interface 'pfe0' */
pfe_netif0: ethernet@10 {
compatible = "nxp,s32g-pfe-netif";
status = "okay";
reg = <10>;
local-mac-address = [ 00 04 9F BE EF 00 ];
nxp,pfeng-if-name = "pfe0";
nxp,pfeng-hif-channels = <PFE_HIF_CHANNEL_0>;
nxp,pfeng-linked-phyif = <PFE_PHYIF_EMAC_0>;
clocks = <&clks S32G_SCMI_CLK_PFE0_TX_SGMII>,
<&clks S32G_SCMI_CLK_PFE0_TX_RGMII>,
<&clks S32G_SCMI_CLK_PFE0_TX_RMII>,
<&clks S32G_SCMI_CLK_PFE0_TX_MII>,
<&clks S32G_SCMI_CLK_PFE0_RX_SGMII>,
<&clks S32G_SCMI_CLK_PFE0_RX_RGMII>,
<&clks S32G_SCMI_CLK_PFE0_RX_RMII>,
<&clks S32G_SCMI_CLK_PFE0_RX_MII>;
clock-names = "tx_sgmii", "tx_rgmii",
"tx_rmii", "tx_mii",
"rx_sgmii", "rx_rgmii",
"rx_rmii", "rx_mii";
phy-mode = "sgmii";
managed = "in-band-status";
};
/* Network interface 'pfe1' */
pfe_netif1: ethernet@11 {
compatible = "nxp,s32g-pfe-netif";
status = "okay";
reg = <11>;
local-mac-address = [ 00 04 9F BE EF 01 ];
nxp,pfeng-if-name = "pfe1";
nxp,pfeng-hif-channels = <PFE_HIF_CHANNEL_1>;
nxp,pfeng-linked-phyif = <PFE_PHYIF_EMAC_1>;
clocks = <&clks S32G_SCMI_CLK_PFE1_TX_SGMII>,
<&clks S32G_SCMI_CLK_PFE1_TX_RGMII>,
<&clks S32G_SCMI_CLK_PFE1_TX_RMII>,
<&clks S32G_SCMI_CLK_PFE1_TX_MII>,
<&clks S32G_SCMI_CLK_PFE1_RX_SGMII>,
<&clks S32G_SCMI_CLK_PFE1_RX_RGMII>,
<&clks S32G_SCMI_CLK_PFE1_RX_RMII>,
<&clks S32G_SCMI_CLK_PFE1_RX_MII>;
clock-names = "tx_sgmii", "tx_rgmii",
"tx_rmii", "tx_mii",
"rx_sgmii", "rx_rgmii",
"rx_rmii", "rx_mii";
phy-mode = "sgmii";
managed = "in-band-status";
};
/* Network interface 'pfe2' */
pfe_netif2: ethernet@12 {
compatible = "nxp,s32g-pfe-netif";
status = "okay";
reg = <12>;
local-mac-address = [ 00 04 9F BE EF 02 ];
nxp,pfeng-if-name = "pfe2";
nxp,pfeng-hif-channels = <PFE_HIF_CHANNEL_2>;
nxp,pfeng-linked-phyif = <PFE_PHYIF_EMAC_2>;
clocks = <&clks S32G_SCMI_CLK_PFE2_TX_SGMII>,
<&clks S32G_SCMI_CLK_PFE2_TX_RGMII>,
<&clks S32G_SCMI_CLK_PFE2_TX_RMII>,
<&clks S32G_SCMI_CLK_PFE2_TX_MII>,
<&clks S32G_SCMI_CLK_PFE2_RX_SGMII>,
<&clks S32G_SCMI_CLK_PFE2_RX_RGMII>,
<&clks S32G_SCMI_CLK_PFE2_RX_RMII>,
<&clks S32G_SCMI_CLK_PFE2_RX_MII>;
clock-names = "tx_sgmii", "tx_rgmii",
"tx_rmii", "tx_mii",
"rx_sgmii", "rx_rgmii",
"rx_rmii", "rx_mii";
phy-mode = "sgmii";
managed = "in-band-status";
};
};
};
};
Here is what Linux prints when the driver loads,
[ 1.139965] phy-s32cc-serdes 40480000.serdes: Using mode 2 for SerDes subsystem
[ 1.150978] phy-s32cc-serdes 40480000.serdes: Unstable RX detected on XPCS1
[ 1.151314] phy-s32cc-serdes 44180000.serdes: Using mode 3 for SerDes subsystem
[ 1.157428] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS1
[ 1.157446] phy-s32cc-serdes 44180000.serdes: Unstable RX detected on XPCS0
...
[ 15.457853] pfeng: loading out-of-tree module taints kernel.
[ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ...
[ 15.469046] pfeng 46000000.pfe: Version: 1.3.0
[ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH
[ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone)
[ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0
[ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000
[ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw
[ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw
[ 15.469151] pfeng 46000000.pfe: netif name: pfe1
[ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01
[ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1
[ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std
[ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02
[ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1
[ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII
[ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4
[ 15.469345] pfeng 46000000.pfe: netif name: pfe2
[ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02
[[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2
15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std
[[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04
0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2
;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII
3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4
2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006
m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e
[ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz
[ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4
O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done
K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed
[ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed
[ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed
15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed
[[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000
0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000
m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000
][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000
[ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes]
F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes]
i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes)
n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101
i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3
s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled
h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created
e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created
d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created
[ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created
15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created
[ 15.457853] pfeng: loading out-of-tree module taints kernel.
[ 15.469032] pfeng 46000000.pfe: PFEng ethernet driver loading ...
[ 15.469046] pfeng 46000000.pfe: Version: 1.3.0
[ 15.469050] pfeng 46000000.pfe: Driver commit hash: M4_DRIVER_COMMIT_HASH
[ 15.469054] pfeng 46000000.pfe: Multi instance support: disabled (standalone)
[ 15.469058] pfeng 46000000.pfe: Compiled by: 12.3.0
[ 15.469085] pfeng 46000000.pfe: Cbus addr 0x46000000 size 0x1000000
[ 15.469093] pfeng 46000000.pfe: nxp,fw-class-name: s32g_pfe_class.fw
[ 15.469098] pfeng 46000000.pfe: nxp,fw-util-name: s32g_pfe_util.fw
[ 15.469151] pfeng 46000000.pfe: netif name: pfe1
[ 15.469158] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:01
[ 15.469166] pfeng 46000000.pfe: netif(pfe1) linked phyif: 1
[ 15.469171] pfeng 46000000.pfe: netif(pfe1) mode: std
[ 15.469184] pfeng 46000000.pfe: netif(pfe1) HIFs: count 1 map 02
[ 15.469192] pfeng 46000000.pfe: SGMII AN enabled on EMAC1
[ 15.469196] pfeng 46000000.pfe: EMAC1 PHY less SGMII
[ 15.469204] pfeng 46000000.pfe: EMAC1 interface mode: 4
[ 15.469345] pfeng 46000000.pfe: netif name: pfe2
[ 15.469351] pfeng 46000000.pfe: DT mac addr: 00:04:9f:be:ef:02
[[ 15.469356] pfeng 46000000.pfe: netif(pfe2) linked phyif: 2
15.469361] pfeng 46000000.pfe: netif(pfe2) mode: std
[[ 15.469373] pfeng 46000000.pfe: netif(pfe2) HIFs: count 1 map 04
0[ 15.469380] pfeng 46000000.pfe: SGMII AN enabled on EMAC2
;[ 15.469384] pfeng 46000000.pfe: EMAC2 PHY less SGMII
3[ 15.469389] pfeng 46000000.pfe: EMAC2 interface mode: 4
2[ 15.469459] pfeng 46000000.pfe: HIF channels mask: 0x0006
m[ 15.469502] pfeng 46000000.pfe: PFE port coherency enabled, mask 0x1e
[ 15.469760] pfeng 46000000.pfe: Clocks: sys=300MHz pe=600MHz
[ 15.469775] pfeng 46000000.pfe: Interface selected: EMAC0: 0xffffffff EMAC1: 0x4 EMAC2: 0x4
O[ 15.470473] pfeng 46000000.pfe: PFE controller reset done
K[ 15.470543] pfeng 46000000.pfe: TX clock on EMAC1 for interface sgmii installed
[ 15.470577] pfeng 46000000.pfe: RX clock on EMAC1 for interface sgmii installed
[ 15.470629] pfeng 46000000.pfe: TX clock on EMAC2 for interface sgmii installed
15.470662] pfeng 46000000.pfe: RX clock on EMAC2 for interface sgmii installed
[[ 15.470842] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34000000
0[ 15.470898] pfeng 46000000.pfe: assigned reserved memory node pfebufs@34080000
m[ 15.470955] pfeng 46000000.pfe: assigned reserved memory node pfebufs@83200000
][ 15.470982] pfeng 46000000.pfe: assigned reserved memory node pfebufs@835e0000
[ 15.476294] pfeng 46000000.pfe: Firmware: CLASS s32g_pfe_class.fw [45040 bytes]
F[ 15.476304] pfeng 46000000.pfe: Firmware: UTIL s32g_pfe_util.fw [23252 bytes]
i[ 15.476316] pfeng 46000000.pfe: [pfe_platform_master.c:3629] PFE CBUS p0x46000000 mapped @ v0xffffffc00c000000 (0x1000000 bytes)
n[ 15.476324] pfeng 46000000.pfe: [pfe_platform_master.c:3634] HW version 0x101
i[ 15.476332] pfeng 46000000.pfe: [pfe_hw_feature.c:93] Silicon S32G3
s[ 15.476340] pfeng 46000000.pfe: [pfe_platform_master.c:3646] Fail-Stop mode disabled
h[ 15.479186] pfeng 46000000.pfe: [pfe_platform_master.c:2783] PFE_ERRORS:Parity instance created
e[ 15.479197] pfeng 46000000.pfe: [pfe_platform_master.c:2798] PFE_ERRORS:Watchdog instance created
d[ 15.479203] pfeng 46000000.pfe: [pfe_platform_master.c:2814] PFE_ERRORS:Bus Error instance created
[ 15.479208] pfeng 46000000.pfe: [pfe_platform_master.c:2827] PFE_ERRORS:FW Fail Stop instance created
15.479214] pfeng 46000000.pfe: [pfe_platform_master.c:2840] PFE_ERRORS:Host Fail Stop instance created
19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created
[0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created
;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000
1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes)
;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ'
3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected
9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready.
m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware
V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel
A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready.
S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"
T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30
[ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0
:[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware
[ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel
I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"
n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3
i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames
t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table
i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping
a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping
l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality
i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features
z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router
e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum
[ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround
P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec
F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging
E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed
s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check
19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check
[[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread
0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan
m[ 19.575398] pfeng 46000000.pfe: FW feature: safety
.[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01.
[ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =.
[ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278
[ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class)
[ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class)
[ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 ()
[ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED
[ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled
[ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled
[ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled
[ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped
[ 19.600089] pfeng 46000000.pfe: HIF1 enabled
[ 19.600319] pfeng 46000000.pfe: HIF2 enabled
[ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped
[ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1
[ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled
[ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1
[ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01
[ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b
[ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s
19.535286] pfeng 46000000.pfe: PFE_ERRORS:Fail Stop instance created
[0[ 19.535290] pfeng 46000000.pfe: PFE_ERRORS:ECC Err instance created
;[ 19.535300] pfeng 46000000.pfe: BMU1 buffer base: p0xc0000000
1[ 19.535388] pfeng 46000000.pfe: BMU2 buffer base: p0x34000000 (0x80000 bytes)
;[ 19.536682] pfeng 46000000.pfe: register IRQ 76 by name 'PFE BMU IRQ'
3[ 19.536851] pfeng 46000000.pfe: Firmware .elf detected
9[ 19.536853] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x000000002bafc76d). Pool ready.
m[ 19.536857] pfeng 46000000.pfe: Uploading CLASS firmware
V[ 19.536865] pfeng 46000000.pfe: Selected FW loading OPs to load 8 PEs in parallel
A[ 19.536866] pfeng 46000000.pfe: BMU_EMPTY_INT (BMU @ p0x00000000a2386541). Pool ready.
S[ 19.556236] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"
T[ 19.571482] pfeng 46000000.pfe: [FW VERSION] 1.8.0, Build: Nov 16 2023, 07:46:11 (nogitaaa), ID: 0x30
[ 19.571773] pfeng 46000000.pfe: EMAC timestamp external mode bitmap: 0
:[ 19.571814] pfeng 46000000.pfe: Uploading UTIL firmware
[ 19.571819] pfeng 46000000.pfe: Selected FW loading OPs to load 1 PEs in parallel
I[ 19.574246] pfeng 46000000.pfe: pfe_ct.h file version"92367c0e25f21f49217a9b08168ad2c8"
n[ 19.575323] pfeng 46000000.pfe: FW feature: drv_run_on_g3
i[ 19.575328] pfeng 46000000.pfe: FW feature: jumbo_frames
t[ 19.575333] pfeng 46000000.pfe: FW feature: software_vlan_table
i[ 19.575337] pfeng 46000000.pfe: FW feature: timestamping
a[ 19.575340] pfeng 46000000.pfe: FW feature: qos_mapping
l[ 19.575344] pfeng 46000000.pfe: FW feature: core_functionality
i[ 19.575348] pfeng 46000000.pfe: FW feature: extended_features
z[ 19.575353] pfeng 46000000.pfe: FW feature: flexible_router
e[ 19.575357] pfeng 46000000.pfe: FW feature: validate_hif_csum
[ 19.575361] pfeng 46000000.pfe: FW feature: err051211_workaround
P[ 19.575365] pfeng 46000000.pfe: FW feature: IPsec
F[ 19.575368] pfeng 46000000.pfe: FW feature: l2_bridge_aging
E[ 19.575373] pfeng 46000000.pfe: FW feature: receive_malformed
s[ 19.575379] pfeng 46000000.pfe: FW feature: ptp_conf_check
19.575384] pfeng 46000000.pfe: FW feature: vlan_conf_check
[[ 19.575389] pfeng 46000000.pfe: FW feature: hash_load_spread
0[ 19.575395] pfeng 46000000.pfe: FW feature: ingress_vlan
m[ 19.575398] pfeng 46000000.pfe: FW feature: safety
.[ 19.577825] pfeng 46000000.pfe: VLAN ID incorrect or not set. Using default VLAN ID = 0x01.
[ 19.577830] pfeng 46000000.pfe: VLAN stats size incorrect or not set. Using default VLAN stats size =.
[ 19.577916] pfeng 46000000.pfe: Software vlan hash table @ p0x20001278
[ 19.578088] pfeng 46000000.pfe: Fall-back bridge domain @ 0x20000a80 (class)
[ 19.578092] pfeng 46000000.pfe: Default bridge domain @ 0x20000a78 (class)
[ 19.579076] pfeng 46000000.pfe: Routing table created, Hash Table @ p0xc00e0000, Pool @ p0xc00e8000 ()
[ 19.579290] pfeng 46000000.pfe: Feature err051211_workaround: DISABLED
[ 19.587357] pfeng 46000000.pfe: MDIO bus 0 enabled
[ 19.593821] pfeng 46000000.pfe: MDIO bus 1 enabled
[ 19.599713] pfeng 46000000.pfe: MDIO bus 2 enabled
[ 19.599725] pfeng 46000000.pfe: HIF0 not configured, skipped
[ 19.600089] pfeng 46000000.pfe: HIF1 enabled
[ 19.600319] pfeng 46000000.pfe: HIF2 enabled
[ 19.600325] pfeng 46000000.pfe: HIF3 not configured, skipped
[ 19.600400] pfeng 46000000.pfe pfe1 (uninitialized): Subscribe to HIF1
[ 19.600407] pfeng 46000000.pfe pfe1 (uninitialized): Host LLTX disabled
[ 19.600833] pfeng 46000000.pfe pfe1 (uninitialized): Enable HIF1
[ 19.600994] pfeng 46000000.pfe pfe1 (uninitialized): setting MAC addr: 00:04:9f:be:ef:01
[ 19.601022] pfeng 46000000.pfe pfe1 (uninitialized): PTP HW addend 0x80000000, max_adj configured to b
[ 19.601031] pfeng 46000000.pfe: IEEE1588: Input Clock: 200000000Hz, Output: 100000000Hz, Accuracy: 10s
Solved! Go to Solution.
chenyin_h
chenyin_h
Hello, @jspace
Thanks for the reply.
I do not mean that your settings are incorrect, the serdes combination used could match the RM description from my opinion.
As you may know, the BSPs are based on NXP's reference board, specially, only for RDB and EVB(including EVB3 and RDB2/RDB3), and some of the serdes combinations that supported by S32G2/G3 could not be supported by the board(since some actual schematic connections), as a result, some of the combinations may not be supported by the default BSP code since it is not supported on the RDB/EVB, howevery, while this combination may be available from hardware perspective on the custom board due different schematic.
Then before applying any serdes combinations on your custom board, I suggest firstly checking the code if could be supported by the BSP, to avoid any error prints like what had shown in your logs.
BR
Chenyin
chenyin_h
I do not have any modifications in U-Boot. Since this messaging comes from the NXP code within U-Boot can you confirm that I should be able to use this configuration?
Serdes0 Lane0 : PCIe
Serdes0 Lane1 : PFE
Serdes1 Lane0 : PFE
Serdes1 Lane1 : PFE
chenyin_h
Hello， @jspace
Thanks for your post.
May I know if you are working with your custom board?
Which version BSP you are working with? How about your serdes settings?(like hwconfig or else)
Thanks for the clarification in advance.
BR
Chenyin
Hey @chenyin_h
Yes it is a custom board.
I'm using,
U-Boot hwconfig is,
serdes0:mode=pcie&xpcs1,clock=ext,fmhz=100;pcie0:mode=rc;xpcs0_1:speed=1G,an=1;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=100;xpcs1_0:speed=1G,an=1;xpcs1_1:speed=1G,an=1
Also u-boot presents this message when in this setting,
Failed to configure XPCS0_1
Failed to update XPCS1 for SerDes0
xpcs0_1 and xpcs 1_0 can't be both SGMII
SerDes1 configuration will be ignored as it's invalid
s32cc_serdes_phy serdes@40480000: Using mode 2 for SerDes subsystem
s32cc_serdes_phy serdes@40480000: Unstable RX detected on XPCS1Hi @jspace ,
According to ethernet enablement user guide, I don't think S32G3 supports all 3 PFE with SGMII mode simultaneously.
Thanks,
XD
@XD I believe that guide is specific to the hardware for the RDB3 which doesn't physically allow the three PFEs to be SGMII connected. The hardware I'm working on doesn't have that physical limitation as long as the chip itself supports the configuration.
