Using 3 Ethernet ports simultaneously on S32G

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Using 3 Ethernet ports simultaneously on S32G

ソリューションへジャンプ
1,325件の閲覧回数
acosara
Contributor IV

We have a customer who wants to use 3 external Ethernet PHYs with the S32G (2 or 3). They would each connect over a RGMII interface. I can see some of the MACs are muxed and share pins, but the IOMux documentation is a bit complicated to follow so I want to make sure we get it right.  Which MACs would they have to connect to in order to get all 3 PHYs working simultaneously? 

0 件の賞賛
返信
1 解決策
1,225件の閲覧回数
acosara
Contributor IV

If you open the pins configurator in S32 Design Studio, you can filter by pin function. There is a column for PFE MAC and GMAC. You can look for all the signals for each MAC in the list and select the pins you want to use them for. When you hover over a pin function, it will tell you if it’s an RGMII or MII signal:

acosara_0-1698171770773.png

 

I was able to get 3 MAC muxed simultaneously by using PFE_MAC0, PFE_MAC1 and PFE_MAC2.

GMAC0 will conflict with 2 other PFE MACs, so you can’t use it if you want to have 3 RGMII MACs.

元の投稿で解決策を見る

0 件の賞賛
返信
6 返答(返信)
1,226件の閲覧回数
acosara
Contributor IV

If you open the pins configurator in S32 Design Studio, you can filter by pin function. There is a column for PFE MAC and GMAC. You can look for all the signals for each MAC in the list and select the pins you want to use them for. When you hover over a pin function, it will tell you if it’s an RGMII or MII signal:

acosara_0-1698171770773.png

 

I was able to get 3 MAC muxed simultaneously by using PFE_MAC0, PFE_MAC1 and PFE_MAC2.

GMAC0 will conflict with 2 other PFE MACs, so you can’t use it if you want to have 3 RGMII MACs.

0 件の賞賛
返信
1,304件の閲覧回数
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Both GMAC and PFE support the RGMII interface. As for 3 PHY's, we understand that they are muxed as follow:

DanielAguirre_0-1697481937136.png

Which can be confirmed if looked under the "IO Signal Table" sheet of the IOMUX file.

For which, it seems as if, under RGMII, there can only be a max of 2 PHY's connected, due to the muxing.

Please, let us know.

0 件の賞賛
返信
1,301件の閲覧回数
acosara
Contributor IV

That doesn't seem to match other documentation. 

Here’s what I found out from Secure File (PR552207):

  • S32G 525FC-BGA supports:

− All 4 MACs can be used in parallel

− Max of 3X RGMII/RMII/MII* interfaces (mux options available for all MACs)

− Max of 4X SGMII interfaces (PFE_MAC0/1/2, GMAC)

The product page also hints that you have up to 4 Ethernet ports and does not mention any cautions or footnotes that there are limitations to the number of ports that are available simultaneously. After all, what's the point of having 4 ports if you can only use 2?

The IO Mux spreadsheet is really confusing to me. The screenshot you captured here to me looks like it describes which power rails are connected to which pins. If I go to the actual IO pins in that file it's a total mess. Pins options show up with missing or conflicting information and there's no way to look up all the pins needed for a type of port, you have to go pin by pin and make sure you got them all. So if I want to see what pins I'll need for GMAC0 for RGMII, for example, I have to look  for all the pins manually by looking at the IO Mux spreadsheet and the user manual at the same time. The pin config feature in Design Studio 32 looks like it might be easier to use, so I'm trying to get that working.

Can you please confirm which documentation is correct? What's a good way to see how the pins are muxed?

0 件の賞賛
返信
1,293件の閲覧回数
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

Thanks for your feedback. It does seem that we have missed this information. We do apologize.

For what we can see, it is true that 3 RGMII interfaces should be available:

DanielAguirre_0-1697487629045.png

From 3 different power domains:

  • VDD_IO_GMAC0
  • VDD_IO_GMAC1
  • VDD_IO_USB

You should be able to filter by power domains and then selecting the interfaces. Could be one way.

As for looking into the muxed pins, the IOMUX file should be one of the available documents. Another, which you are already looking, is the Config Tools under S32 Design Studio.

Still, could be that we are misunderstanding your request. If so, we apologize.

Please, let us know.

0 件の賞賛
返信
1,281件の閲覧回数
acosara
Contributor IV

I can't find anywhere in the documentation what are the signals required to run a RGMII interface. Datasheet, RM all point to IOMUX when it comes to individual signals, but IOMUX does not break it down into type of Ethernet interface (MII vs RGMII for example) (just by MAC). The S32 Design Studio, while much easier to use than the IO MUX spreadsheet, has the same problem, it will not tell me which signals for each MAC in order to use RGMII vs MII. 

What I'm trying to achieve is to know what pins I need to configure as what function, in order to get 3 RGMII MACs working at the same time. 

0 件の賞賛
返信
1,269件の閲覧回数
Daniel-Aguirre
NXP TechSupport
NXP TechSupport

Hi,

RGMII is a standard, for which the overall required signals should be same regardless of the chip/family/supplier. The following is mentioned under the following link (Media-independent interface - Wikipedia

DanielAguirre_0-1697563757983.png

Which should be the signals required for an RGMII interface. The name could vary, but the functionality should remain the same.

The IOMUX file shows the functionality regardless of the interface, since the MACs can work with MII/RMII/RGMII. Depending on which interface you are working with, you need to select the signals you require to use.

Again, we could be misunderstanding this last request. If so, we apologize.

Please, let us know.

0 件の賞賛
返信