Hi Joey_z,
I got failed after update device tree.
I upload my s32g.dtsi siul2 part to BSP43 version as attached.
Also I modify our device tree as below:
fdts/s32gxxxa-rdb.dtsi
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&custom1_pins, &custom2_pins>;
};
&pinctrl {
u-boot,dm-pre-reloc;
custom1_pins: custom1_pins {
custom1_grp0 {
pinmux = <S32CC_PINMUX(174, FUNC0)>;
input-enable;
};
custom1_grp1 {
pinmux = <S32CC_PINMUX(37, FUNC0)>;
output-enable;
};
custom1_grp2 {
pinmux = <S32CC_PINMUX(171, FUNC0)>;
bias-pull-down;
output-enable;
};
};
custom2_pins: custom2_pins {
custom2_grp0 {
pinmux = <S32CC_PINMUX(183, FUNC0)>;
input-enable;
};
custom2_grp1 {
pinmux = <S32CC_PINMUX(28, FUNC0)>;
output-enable;
};
custom2_grp2 {
pinmux = <S32CC_PINMUX(173, FUNC0)>;
bias-pull-down;
output-enable;
};
};
In our hardware design, both PK_13 (173) and PK_11 (171) GPIOs from the SoC are connected to the EN pin of the MPQ5068GQV-AEC1-Z. A 10 Kohm pull-down resistor is also connected to the EN pin
SoC GPIO: PK_13 (173) ─┬──> EN pin of MPQ5068GQV-AEC1-Z
|
R (10kΩ pull-down)
|
GND
SoC GPIO: PK_11 (171) ─┬──> EN pin of MPQ5068GQV-AEC1-Z
|
R (10kΩ pull-down)
|
GND
Below is my test log
// Port Module SSS Addr Function
// PK_13 SIUL_OFFCC 0000_0000 0x440104F4 GPIO[173]
=> md.l 0x440104F4 1
440104f4: 00010000
=> gpio toggle siul2-gpio@4009d700173
gpio: pin siul2-gpio@4009d700173 (gpio 173) value is 1
Warning: value of pin is still 0
=> md.l 0x440104F4 1
440104f4: 00202000
// Port Module SSS Addr Function
// PB_12 SIUL_CC 0000_0000 0x440104F4 GPIO[28]
=> md.l 0x4009C2B0 1
4009c2b0: 00200000
=> gpio toggle siul2-gpio@4009d700028
gpio: pin siul2-gpio@4009d700028 (gpio 28) value is 1
=> md.l 0x4009C2B0 1
4009c2b0: 00280000
Thanks