S32G3 Bootloader launch core0 and Core1

[xlfd_1981]

hi NXP erperts

I am currently debugging a bootloader to bring up core0 and core1. The core0 can be released from reset and can be lanutched, but core1 fail to start running.

Using the UDE debug tool, core1 can be successfully brought up. In my bootloader EB Configuration, I have already configured the reset handler address and load address for both core0 and core1. How should I proceed with further debugging? how can i debug the bootloader?

i am also test the IPCF_Example_multi_instance_S32G399A project, but this project the core0 and core1 both failed.

thanks.

[chenyin_h]

Hello, @xlfd_1981 

I feel sorry for your inconvenience.

Commonly, in this community board, we support the basic usage of all software packages, hardware specifications provisioned by NXP, also, we support issues directly found in using demo/sample code within  the software packages, etc.

For specific or customization requirement, we usually suggest raising support ticket via the support.nxp.com, since it is private channel, and is more convenient for sharing the code/project.

Currently, there are not such kind of demo which could directly support your requirement, only the code in AN1350 is a little similar but it also involved A53 cores, it may be possible to disable the A53 part to simulate your requests, not sure if you have referenced it.

For your status, in order for help you directly for debugging your issues, I suggest directly raising a private ticket via support.nxp.com, then sharing your bootloader and applications(M7_0 and M7_1), we could help to check it.

BR

Chenyin

[chenyin_h]

Hello, @xlfd_1981 

Thanks for your reply.

May I know how you creating the IVT, have you included DCD while trying booting from the QSPI?

I am not very sure of your design, you are using the bootloader(M7_0) to load core0.bin and core1.bin(IPCF instances) to the corresponding core, or other kind of implementation?

BR

Chenyin

[chenyin_h]

Hello, @xlfd_1981 

Thanks for your post.

Would you mind providing more information about your test?

1. It is done on a S32G3 custom board or RDB3/EVB3 from NXP?

2. Where is the bootloader from? it is a custom one or from NXP, if from NXP, which version?

3. It is mentioned that core0&1 are used, may I know if they are M7_0 and M7_1 or other combination?

Commonly, the bootloader is running on the M7_0, it could be debugged directly with your debugger, not different from other M7 applications.

BR

Chenyin

[xlfd_1981]

Chenyin

We are currently working on the RDB3 platform, developing a bootloader based on your IPCF Multi-Core Demo (v4.10.0). We're encountering an issue during the boot process of Core1 and would appreciate your assistance.

Current Setup:

1. Our bootloader is developed based on your demo project(UM_BOOTLOADER_Rev_2023.02) and configured via EB.
2. When debugging with UDE:
   • Data exists in both Core0 and Core1 memory regions 
   • Code successfully jumps to Core0's Reset_Handler 
3. However, we noticed that:
   • The SRAM area used by Core1 (e.g., 0x34680000) gets cleared to zero 
   • As a result, Core1 fails to start 

Questions:

• Who triggers this SRAM clearing?
  • Is it caused by UDE?
  • Or is it part of the reset behavior?
  • Could it be due to some initialization code in the bootloader?

1. In addition, in the function Sys_StartSecondaryCores(), we set:

IP_MC_ME->PRTN0_CORE1_ADDR = 0x34780000;

Could you please confirm what this address should point to:

• Should it be the load address of the Core1 image in SRAM (i.e., the location of .intc_vector)?
• Or should it be the vector table offset (VTOR)?

Our linker script shows that .intc_vector is located at 0x34780400, while the image starts at 0x34680000.

Thank you very much for your support!
If needed, I can provide .map files, .ld scripts, or screenshots for further analysis.

Best regards,

[xlfd_1981]

chengyin

In addition, my IPCF codes, please check,

it will be compiled to core0.bin and core1.bin 

[xlfd_1981]

chengyin

i update my debugging results below,

It might be related to the bootloader. When debugging with UDE, the ELF file is downloaded into memory and we can see that the Core1 region has valid data. However, after a power cycle — where the system boots from Flash running the bootloader code — and using UDE to observe the Core1 memory area, we find that the data has been cleared to zero. Could this be caused by the bootloader?

Regards

[xlfd_1981]

NXP experts

It's been many days and I still haven't received a response to my question. Let's keep it simple now: please provide a demo program that can start both core0 and core1 using the bootloader. I need both the bootloader project and the application project. Also, please let me know if there are any special requirements for generating the blob file. I will use your demo to verify whether core0 and core1 can be started properly.

The issue I'm facing now is that the image for core1 can be loaded, but core1 just won't start. I don't know whether the problem is with the startup code or if core1 simply isn't being triggered at all. There are also no registers available to check if it started. Please help me by providing a demo and suggestions. This is quite urgent. Thank you very much.