S32G || CAN controller module clock details

[Diwakar07]

Hi Team,  

  I have below questions regarding the CAN controller module clock,
1. Does the clock for the CAN controller module is provided from the internal PLLs in SOC?

2.  what is the PLL frequency tolerance (long-term jitter or phase skew) ? 
  Can you help with above queries ? 

[chenyin_h]

Hello, @Diwakar07 

Thanks for the post.

The clock for the CAN controller module is provided from the internal PLLs, as shown below:

chenyin_h_1-1741860363217.png

The PLL Jitter tolerance value could refer to table27 on S32G3 Data Sheet as below:

chenyin_h_2-1741860499927.png

I hope it will help.

BR

Chenyin