Divider configuration update is pending for CLKOUT0

[BalaAB]

I am trying to generate an clock out of 1MHz on CLKOUT0 on S32G274A with the below configuration but divider configuration update is pending continuously.

MUX_1_CSC : SELCTL -- clk_src_2, FCG -- 0, CG -- 1

MUX_1_DC_0 : DE -- 1, DIV -- 0x27

MUX_1_DIV_UPD_STAT : 1

Please let me know as how to resolve this issue.

[Daniel-Aguirre]

Hi,

Which RTD version are you using? For what we can see, you might not be using one, but we would like confirmation. 

Also, are you using any NXP development board? Or is this a custom board?

Please, let us know.

[BalaAB]

Hi,

I am not using any packages of drivers, its my own piece of code. Testing is done on NXP development board S32G-VNP-RDB2 REVC.

I hope i have answered your question correctly.

[Daniel-Aguirre · Accepted solution]

Hi,

Thanks for your feedback. Seen the S32G2 RM, we found the following note [Page 979, S32G2 Reference Manual, Rev. 7, February 2023]:

Which mentioned that if the DIV_STAT bit stays at 1, then the problem might be related to the selected clock source, and 2 steps are shown on how to change if that happens.

As for the configuration the mux itself, we see that Figure 130 and 131 under the RM [Page 1161 & 1163, S32G2 Reference Manual, Rev. 7, February 2023] show the expected flow to configure the CLK switch, we understand that not all steps are being followed under the pseudo-code shared with us.

Can you confirm that following the steps provide a different outcome?

Please, let us know.

[BalaAB]

Hi Daniel,

The steps mentioned in Figure 130 and 131 under the RM [Page 1161 & 1163, S32G2 Reference Manual, Rev. 7, February 2023], has supported to resolve the issue.

Thanks a lot.