Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug

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Core1 Not Starting on S32DS399 Multi-Core System with UDE Debug

457 次查看
xlfd_1981
Contributor III
Dear NXP Support Team,

I hope this message finds you well.
I am currently working on a multi-core application on the NXP S32DS399 device using UDE (Universal Debug Engine) for debugging and flashing. I have encountered an issue where only Core0 is entering its reset handler after system reset, while Core1 does not seem to start at all.
Here are the details of my setup and observations:
- Device: NXP S32DS399- IDE/Debugger: PLS UDE (Universal Debug Engine)
- Cores: Cortex-M7 x4 (Core0 ~ Core3)
- Issue: After reset, only Core0 enters its reset handler (`reset_handler`), but Core1 does not appear to execute any code.
What I have tried so far:- Verified that the ELF file for Core1 is correctly loaded into memory via UDE's Memory Browser.- Attempted manual PC/SP setup in UDE for Core1 and resumed execution, but no response.- Checked the linker script for Core1 — it defines a valid vector table and entry point.- Suspect that there may be a hardware-level configuration required (e.g., register settings or core release mechanism) to allow Core1 to start executing after reset.
Could you please help me with the following?
1. What are the necessary steps to properly initialize and start Core1 on the S32DS399?2. Is there a specific register or module (e.g., MU, RCRU, etc.) that needs to be configured to "release" Core1 from reset?3. Do you have any example code or documentation showing how to boot multiple cores on this platform?4. Are there any known issues or limitations when using UDE for multi-core debugging and flashing on this device?
Any guidance or reference materials would be greatly appreciated.
Thank you very much for your support!
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423 次查看
xlfd_1981
Contributor III

hi NXP Support Experts

I'd like to add one more point: the multi-core license is already installed. I have verified this.
Could you please provide me with a demo showing how to start Core 1, Core 2, and Core 3 from Core 0?
It would be greatly appreciated if you could guide me on how to modify the UDE script to enter the reset handler for Core 1, Core 2, and Core 3.

Best Regards

Sandy Li

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carlos_o
NXP TechSupport
NXP TechSupport

Hi @xlfd_1981,

For Multicore applications you need to implement a Bootloader

You could find an application note about this topic as Enabling Multicore Application on S32G2 using S32G2 Platform Software Integration, you could review it to learn how to create and configure the bootloader for your application.

Also, there is a figure that shows how is the boot flow working on the device (the application note and the figure includes the implementation of the BSP, but you could only use the M7 cores if you want)

carlos_o_0-1749755652235.png

 

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407 次查看
xlfd_1981
Contributor III

hi @carlos_o 

Thanks your responce, i have one question, please.

Do you mean that the multi-core system can only be initialized through the bootloader, and not started via the debugger (UDE)? But debugging with UDE is still possible, right?

 

Regards

Sandy

 

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carlos_o
NXP TechSupport
NXP TechSupport

Hi @xlfd_1981,

NXP gives scripts to initialize a multicore debugging with Lauterbach in the GoldVIP package, in the case of the UDE you need to review with PLS to give you the corresponding script to do it.

The only debugging information we have with the UDE is the following HOWTO: Install PLS UDE debugger plug-in into S32 Design Studio

 

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