Hi,
I have to protect part of my code against interruption (i.e update sw_fifo's pointers).
I see lots of words on web, goods and bads, but at least i need to have some kind of synthesis.
i see the following :
#define ENABLE_INTERRUPTS() __asm volatile ("cpsie i" : : : "memory");
#define DISABLE_INTERRUPTS() __asm volatile ("cpsid i" : : : "memory");
Some time with couter... i feel ok with this part.
Some time i also see dsb and isb usage right after disabling interrupt. I think it's more related to S32K14x... Can you confirm me that i don't need to do use these instructions?
Both usage can be found on Project exemple FreeRtos_s32k116 and flexcan_encrypted_s32k116
Thanks in advance for your clarifications
Solved! Go to Solution.
Hi @francoisdugue,
I believe this is explained in
ARM Cortex ™ -M Programming Guide to Memory Barrier Instructions Application Note 321
https://documentation-service.arm.com/static/5efefb97dbdee951c1cd5aaf?token=
4.8 Disabling interrupts using CPS and MSR instructions
4.7 Enabling interrupts using CPS instructions and MSR instructions
BR, Daniel
Hi Daniel,
I'll have a deep look on it.
Thank you for the link
Hi @francoisdugue,
I believe this is explained in
ARM Cortex ™ -M Programming Guide to Memory Barrier Instructions Application Note 321
https://documentation-service.arm.com/static/5efefb97dbdee951c1cd5aaf?token=
4.8 Disabling interrupts using CPS and MSR instructions
4.7 Enabling interrupts using CPS instructions and MSR instructions
BR, Daniel