eMIOS OPWFMB mode initialization using S32DS SDK

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eMIOS OPWFMB mode initialization using S32DS SDK

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dan_teodorescu
Contributor III

Hello,

The MPC5777C Reference Manual recommends initializing the eMIOS UC counter (CNT register) to a value between 1 and the period (B register). From MPC5777CRM section 36.6.1.1.14:

When entering OPWFMB mode coming out of GPIO mode, the internal counter value is
not within that range then the B match will not occur causing the channel internal counter
to wrap at the maximum counter value which is 0xff_ffff for a 24-bit counter. After the
counter wrap occurs it returns to 0x1 and resume normal OPWFMB mode operation.
Thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to
B1 register value range when the OPWFMB mode is entered.

The S32DS SDK eMIOS PWM driver does not appear to explicitly set the CNT register during initialization (EMIOS_DRV_PWM_InitMode() and downstream functions). Is this intentional or should the SDK driver be updated to address the reference manual requirement?

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truongtranvan
NXP Employee
NXP Employee

Hi dan.teodorescu‌,

In the MPC5777CRM wrote that:

1. The eMIOS UC counter (CNT register) is a read-only register => It mean we cannot set value for them.

2.  When entering another operation mode, this register is automatically cleared.

So, eMIOS_PWM driver cannot set value for CNT register during initialization for OPWFMB mode. Further, the function EMIOS_DRV_PWM_InitMode() has set value for B register before entering OPWFMB mode with the desire to avoid the above problem.

Thanks & Best regards,

Truong Tran.

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dan_teodorescu
Contributor III

Hi truongtranvan‌,

I found the description you mentioned regarding the CNT register being read-only in non GPIO mode, in MPC5777CRM section 36.5.3 (page1399). However, the same section claims "When entering some operation modes, this register is automatically cleared (refer to the “UC Modes of Operation” section for details)."

However, the only note on this topic in the OPWFMB mode, is what I stated in my original post "...Thus in order to avoid the counter wrap condition make sure its value is within the 0x1 to B1 register value range when the OPWFMB mode is entered."

We use this code in a safety-critical application so it is essential that the eMIOS perform correctly. Would it make sense to update the PWM driver to initialize the CNT register prior to entering the OPWFMB, by calling EMIOS_SetUCRegCNT() as shown below?

static status_t EMIOS_DRV_PWM_InitPeriodDutyCycleMode(uint8_t emiosGroup,
uint8_t channel,
emios_opwfm_param_t *opwfmParam)
{
uint8_t restChannel = 0U;
    bool restValidate = EMIOS_ValidateChannel(channel, &restChannel);
DEV_ASSERT(emiosGroup < EMIOS_NUMBER_GROUP_MAX);
DEV_ASSERT(restValidate == true);
DEV_ASSERT(opwfmParam != NULL);
DEV_ASSERT((opwfmParam->mode == EMIOS_MODE_OPWFMB_FLAGX1) || \
(opwfmParam->mode == EMIOS_MODE_OPWFMB_FLAGX2));

/* Validate opwfm parametter */
DEV_ASSERT((opwfmParam->periodCount <= EMIOS_OPWFMB_MAX_CNT_VAL) && \
(opwfmParam->periodCount > EMIOS_OPWFMB_MIN_CNT_VAL));

DEV_ASSERT(opwfmParam->dutyCycleCount <= opwfmParam->periodCount);

/* Valid Opwfmb with channels supported */
if (EMIOS_ValidateMode(emiosGroup, restChannel, (uint8_t)EMIOS_GMODE_OPWFMB) == false)
{
DEV_ASSERT(false);
}

/* Configure registers */
eMIOS[emiosGroup]->UC[restChannel].C = 0UL; /* Disable channel pre-scaler (reset default) */
if ((uint8_t)opwfmParam->outputActiveMode == (uint8_t)EMIOS_NEGATIVE_PULSE)
{
EMIOS_SetUCRegA(emiosGroup, restChannel, opwfmParam->dutyCycleCount);
}
else
{
EMIOS_SetUCRegA(emiosGroup, restChannel, opwfmParam->periodCount - opwfmParam->dutyCycleCount);
}

EMIOS_SetUCRegB(emiosGroup, restChannel, opwfmParam->periodCount);
EMIOS_SetUCRegCNT(emiosGroup, restChannel, 1U); /* See: https://community.nxp.com/message/1101052 */
EMIOS_SetUCRegCEdpol(emiosGroup, restChannel, (uint32_t)opwfmParam->outputActiveMode);
EMIOS_SetUCRegCMode(emiosGroup, restChannel, (uint32_t)opwfmParam->mode);
EMIOS_SetUCRegCUcpren(emiosGroup, restChannel, opwfmParam->internalPrescalerEn ? 1UL: 0UL);
#if defined(FEATURE_EMIOS_PRESCALER_SELECT_BITS)
EMIOS_SetUCRegC2UCEXTPRE(emiosGroup, restChannel, (uint32_t)opwfmParam->internalPrescaler); /* Pre-scale channel clock by internalPrescaler +1 */
EMIOS_SetUCRegC2UCPRECLK(emiosGroup, restChannel, 0UL); /* Prescaler clock selected*/
#else
EMIOS_SetUCRegCUcpre(emiosGroup, restChannel, (uint32_t)opwfmParam->internalPrescaler); /* Pre-scale channel clock by internalPrescaler +1 */
#endif

return STATUS_SUCCESS;
}
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truongtranvan
NXP Employee
NXP Employee

Hi dan.teodorescu‌,

Your opinion is very good, but add the function EMIOS_SetUCRegCNT is not necessary because internal counter is cleared when entering GPIO mode. In the function EMIOS_DRV_PWM_InitPeriodDutyCycleMode will clear UC register before configures and entering OPWFMB mode by this line of code eMIOS[emiosGroup]->UC[restChannel].C = 0UL; /* Disable channel pre-scaler (reset default) */. That mean it will entering GPIO mode and UC CNT will be cleared before configures and entering OPWFMB mode.

Thank you.

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dan_teodorescu
Contributor III

Hi truongtranvan‌,

I apologize for not noticing earlier that there is a discrepancy between how the GPIO mode clears the count register and what is a valid value for the register in OPWFMB mode. The register is cleared in GPIO mode, but the OPWFMB mode requires that it be initialized to a value between 1 and the value of the B1 register. Having GPIO mode initialize it to 0 does not meet this requirement. In this case I believe that an explicit CNT register initialization is necessary.

Thank you,

Dan

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dan_teodorescu
Contributor III

Hi truongtranvan‌,

You are correct. According to MPC5777CRM section 36.6.1.1.1 (page 1422), "In GPIO mode, all input capture and output compare functions of the Unified Channel are disabled, and the internal counter (EMIOSCNTn register) is cleared and disabled." I will remove the line I added in my copy of the driver.

Thank you, Dan

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