Thank Daniel.
I used these functions:
void SlowRUNmode_FIRC_48MHz(void)
{
SCG->RCCR=SCG_RCCR_SCS(3) /* FIRC as clock source*/
|SCG_RCCR_DIVCORE(0b00) /* DIVCORE=0, div. by 1: Core clock = 48/1 MHz = 48 MHz*/
|SCG_RCCR_DIVBUS(0b00) /* DIVBUS=0, div. by 1: bus clock = 48 MHz*/
|SCG_RCCR_DIVSLOW(0b01); /* DIVSLOW=1, div. by 2: SCG slow, flash clock= 24 2/3 MHz*/
while (((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT ) != 3) {}
/* Wait for sys clk src=FIRC */
}
void FIRC_init_48MHz(void)
{
SCG->FIRCCSR = 0x00000000; //FIRCCEN=0: SIRC is disabled (default) for write
SCG->FIRCDIV = 0x00000101; //FIRCDIV1 & FIRCDIV2 divide by 1, max in HSRUN/RUN is 48MHz
SCG->FIRCCFG = 0x00000000; //Range 48MHz
SCG->FIRCCSR = 0x00000001; //LK=0: FIRCCSR can be written
//FIRCCEN=1: Enable SIRC, FIRCSEL = 0 ->Fast IRC is not the system clock source
while(!(SCG->FIRCCSR & SCG_FIRCCSR_FIRCVLD_MASK)); // Wait for FIRC valid
}
As mentioned in RM (pag.541) when there is FIRC clock it is should set the slow run mode. With the functions that I wrote above, I have the Bus Clock equal to 48MHz and the clock of ADC equal to FIRCDIV2 that is equal to 48MHz with ADIV = 0.
In this configuration I should have both fADC, fBUS equal to 48MHz. I would know if the configuration for FIRC clock is correct in order to have a correct conversion time from the formula of ADC.
Best regards
Paola
