xgate memory confusion

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xgate memory confusion

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rahulkrishna
Contributor IV

Hi,

For S12XEQ512 the details of the memory map are

S12X:

Flash 512K Address range: 0x78_0000 to 0x7F_FFFF.

RAM 32k Address Range: 0x0F_8000 to 0x0F_FFFF.

Xgate:

Flash 30k: 0x78_8000 to 0x78_0800

RAM: 32k: 0F_8000 to 0x0F_FFFF

If I convert xgate lower flash address 78_0800 in to the local memory map it is E0-0800. So, the PPAGE register is E0 and the local memory is 0x0800.

But the paged flash memory map is valid from 0x8000 to 0xC000. What is this addres E00800?

In prm i found the following address

PAGE_E0_0     = READ_ONLY   DATA_FAR IBCC_FAR  0xE08000 TO 0xE087FF; /* cannot be mapped to XGATE; XGATE sees registers here */

PAGE_E0       = READ_ONLY   DATA_FAR IBCC_FAR  0xE08800 TO 0xE0BFFF ALIGN 2[1:1]; /* is also mapped to XGATE:  0x0800..0x3FFF*/  

But i am not able to find the address 0xE00800. What is the mistake i am doing?

 

Thanks and regards

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lama
NXP TechSupport
NXP TechSupport

The understanding of the memory addressing is in understanding of the range of the address and instruction used for addressing. Please look into attached memory map to better understand.

If the offset of the address is between 8000~BFFF the FLASH is accessed for code reading. Address is created by PPAGE_offset. This addressing mode can be used also for data access in the paged flash but it requires more complicated approach so it is better to use global addressing GPAGE_offset for data addressing in the flash. If global addressing instruction is used then offset does not have sense and address is GPAGE_offset offset is from range 0000~FFFF. If you look into the mentioned excel sheet you will recognize offset windows for page mode addressing (column J)

XGATE is visible on short (16bit) addresses in the internal ram. However, there is a part of flash covered by XGATE. What XGATE sees at 800~3FFF, 4000~7FFF the CPU sees at E0B800~E0BFF, E1_8000~E1BFFF using PPAGE_OFFSET addressing mode or 78_0800~78_3FFF, 78_4000~78_7FFF using global addressing mode and instructions.

I have put here a few examples which can help you. Some more can be found at https://community.freescale.com/docs/DOC-95116

Sharing pointers between CPU and XGATE:

In order to share data between XGATE and CPU you have to either use shared variables or you have to perform correct conversions between pointers. We are not allowed to share the pointers between S12CPU and XGATE directly but we can use this workaround:

The 16bit offset of far (global) address on S12CPU is the same as 16bit address on XGATE. So, we can share long int variable that is re-typed to far pointer when used on S12CPU and then we can take the lower part of this variable and re-type it to standard “near” pointer on XGATE core.

A simple example program XET256 - Shared pointers - CW51.zip can be found in attachment.

I hope this helps.

If you see this answer as correct answer please mark it as correct and helpful to help others to find good answers faster. Thank you in advance.

Best Regards, Ladislav

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177 Views
lama
NXP TechSupport
NXP TechSupport

The understanding of the memory addressing is in understanding of the range of the address and instruction used for addressing. Please look into attached memory map to better understand.

If the offset of the address is between 8000~BFFF the FLASH is accessed for code reading. Address is created by PPAGE_offset. This addressing mode can be used also for data access in the paged flash but it requires more complicated approach so it is better to use global addressing GPAGE_offset for data addressing in the flash. If global addressing instruction is used then offset does not have sense and address is GPAGE_offset offset is from range 0000~FFFF. If you look into the mentioned excel sheet you will recognize offset windows for page mode addressing (column J)

XGATE is visible on short (16bit) addresses in the internal ram. However, there is a part of flash covered by XGATE. What XGATE sees at 800~3FFF, 4000~7FFF the CPU sees at E0B800~E0BFF, E1_8000~E1BFFF using PPAGE_OFFSET addressing mode or 78_0800~78_3FFF, 78_4000~78_7FFF using global addressing mode and instructions.

I have put here a few examples which can help you. Some more can be found at https://community.freescale.com/docs/DOC-95116

Sharing pointers between CPU and XGATE:

In order to share data between XGATE and CPU you have to either use shared variables or you have to perform correct conversions between pointers. We are not allowed to share the pointers between S12CPU and XGATE directly but we can use this workaround:

The 16bit offset of far (global) address on S12CPU is the same as 16bit address on XGATE. So, we can share long int variable that is re-typed to far pointer when used on S12CPU and then we can take the lower part of this variable and re-type it to standard “near” pointer on XGATE core.

A simple example program XET256 - Shared pointers - CW51.zip can be found in attachment.

I hope this helps.

If you see this answer as correct answer please mark it as correct and helpful to help others to find good answers faster. Thank you in advance.

Best Regards, Ladislav

176 Views
rahulkrishna
Contributor IV

Thank you very much for the detailed mail. It will take some time for me to understand and i think it will also be a difficult one to grasp the concept. I will try my best to understand it. In any case thank you very much for the information you shared.

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