Hello Jeff,
I think we are referring to the same document. The revision 13 I mention is for the whole ZIP file and is not for individual files.
There are differences between a "spec clarification" and an "erratum". The second one means that the MCU does not behave as specified whilst the first one means that we had all the elements already, but that because confusion was reported, the manual was updated to avoid that confusion.
Now coming to 1...
I didn't know I would have the revelation at 4am, but I do understand fine now.
The SCI module has only ONE interrupt vector. By this, it means that Errors have to share the same interrupt subroutine as Normal transmission.
Then, I tought about... What is an Over Run condition ?
The OR condition means that the module received a new data but data previously received was not read. And that is the key! "The module received a new data" so an interrupt is generated when OR occurs, this is the interrupt occuring when the data is received.
An OR cannot occur unless you have a valid reception.
If the OR flag itself was to generate an IRQ, it would mean you would get a DOUBLE interrupt to the same vector in a case of over run:
- you would get the Receiver Full, because after all a VALID data was received,
- and the OR condition.
But which Interrupt source should be set first ? I mean to be in a case of OR, you need to have received and overwritten the previously received data, therefore you have to get Receiver Full first.
But you need to know before reading the receiver data that you skipped at least one to know where to put that data.
These two last conditions are contradictory, and it would be highly in-efficient to generate two IRQ back to back to execute the same ISR !
So what does make sense for the software ?
As OR cannot occur without RDRF, then you only need to generate an IRQ for RDRF.
Then, when the software enters the ISR, it can check if the valid value has overwritten the previous.
Generating an IRQ for each bit would only make sense either if RDRF and OR were independant events (which it will never be) or if we had a separate interrupt vector for Receiving and for Errors (like for the msCAN).
#1 - Therefore it is logical and normal that OR itself does not generate an ISR
On the second point.
Clearing a flag has a certain procedure. If RDRF is cleared and nothing has been done to clear OR, then RDRF is cleared when OR is set.
#2 - It means that the error condition does not clear by itelf and you need user intervention.
(May be the user receives by bursts and only want to check, out of the ISR that the data in the buffer is correct)
I hope it is now as clear for you as it is for me.
The document (S12SCIV2.pdf and the ZIP archive) will still have to be changed for the reason I gave previously.
Regards,
Alban.