config FCLKDIV

[imajeff]

I get baffled and confused every time I try to make sense of docs for calculating FCLKDIV. Using DP256B (if that ever makes a difference). I'm going to go over the example below to verify how it's done.

I suppose "FDIV" always refers to FDIV bits [5:0] (not concerned with PRDIV8).

Figure 4-1 looks incomplete, yet anywhere that I should find details it just says look at 4-1 for all my answers (yeah-right). What clk source am I starting with? I think it means OSCCLK. I guess PLL only matters if Tbus exceeds certain limits.

First, what goes on left side of the equals? There are places where the expression starts with '=' so I see no indication what the result represents. You just have to know? Then why am I reading the stupid instructions?

Questions about this wierd expression "=PRDCLK[MHz]*(5+Tbus[uS])"... what goes on left side; is it the value so far for FDIV? I'll assume the [MHz] and [uS] means I can enter 24 and 0.5 in a calculator when the value is really 24,000,000 and 0.0000005 respectively. Note, that confuses me sometimes because I already have the real value in the calc. I also wonder if there is some complex reason why I'm checking if the result is an "integer". How accurate do I need to be in decimal places? Since I'm multiplying with Tbus < 1uS it seems not likely to ever be a whole integer. But if it does come out, it's hard to visualize why I treat it differently. I see no explanation. Hopefully I don't want to know, because I don't.

I try to assume that value n in FDIV[5:0] would cause divide by n+1, but I don't see that described anywhere. It's only possibly derivable from the cryptic expressions in Fig 4-1.

Can I assume all is the same for EEPROM's ECLKDIV?

=== Example seems to work ====
For my board, I start with:

oscillator = 16 MHz (xtal rating)
Fbus = 24 MHz (PLL set 3/2)
-therefore Tbus ~= 1/24 [uS] (or 0.0416666667 uS)

1. Since 16 > 12.8, I divide by 8
PRDIV8 = 1
PRDCLK = 2 MHz

2. Since 2*(5+1/24) is not rounded, I don't subtract 1
FDIV = 10

3. FCLK (between 150 kHz and 200 kHz): 2e6/(1+10)
FCLK = 181.818 kHz

4. Since (1/181,818 + 1/24) > 5 uS, FDIV is OK


Using my assumptions I end up with PRDIV8=1, FDIV=10 (0x0a), therefore FCLKDIV = (PRDIV8_MASK | 0x0a) = 0x4a.

Whew, I hope this helps people, as well as gets more explanation out of people who know what's going on.

Message Edited by imajeff on 05-10-200604:18 PM

[imajeff]

I've got to ask...

My previous example shows at 16 MHz, FCLKDIV = 0x4a. Now instead of 10, what if I put 0x49? That calculates to FCLK of 200 kHz:

PRDCLK / (1 + FDIV)
2 MHz / (1 + 9) = 200k

Is that a problem? It seems more efficient to me, yet the docs say to settle for 181.818 kHz because of that strange algorithm.

[Technoman64]

I think that they would rather have the value fall in between the min and max frequency to insure FLASH longevity. This is just my thoughts based on the section regarding calculating this value.