FCLKDIV register reconfiguring

[imajeff]

If I
1. configure FCLKDIV for no PLL
2. load some Flash
3. enable PLL (bus jumps 8 to 24 MHZ)

Does FCLKDIV (esp. FDIVLD) stay the same and therefore cause danger in not noting that it may need re-initialized?

[Alban]

Hi Imajeff,

On S12 like 9S12DT128, FDIVLD means "Register has it been written since last Reset".

Therefore if you change between reset the bit has no reason to change status.

The divider is WRITE ONCE !!! Be careful.

Up to the user to know what's he's doing...

Alban.

[Technoman64]

The FLASH Clock is taken from the main OSC frequency. You set the FLCKDIV based on the OSC input frequency. There are parameters that must be met in regards to the OSC input frequency, Actual BUS Frequency, and FCLKDIV. If memroy serves me right this formula is listed in the FLASH section of the user guide.

I believe the only time there would be an issue after enabling the PLL and going to a higher bus frequency is when the OSC input is a very low frequency and the PLL steps it way up near max for the device.

Please verify this with the FLASK BLock user guide for your device.

From the FLASH block guide on DP256 device

"These algorithms are controlled by a state machine whose timebase FCLK is derived from the oscillator clock via a programmable divider."

Message Edited by Technoman64 on 05-10-200603:08 PM

[mke_et]

I would doubt it stays the same, since the divider for fclk is 'downstream', anything you do upstream is going to affect it.  But if you need an answer for sure, you'd need one of the Freescale guys to answer.

If I had a routine that could operate under different conditions, I'd have it check the conditions and caculate what fclkdiv needs to be...  That is, asuming you have a reference somewhere, like always a specific crystal or something.