Hi Steve,
Thank you for more details.
Do you use PLL for generating bus clock or not?
If you use PLL, there missing low-pass filter between XFC and VDDPLL pins at your schematic.
If you don’t use PLL, the XFC pin has to be connected to VDDPLL pin.
Please look at Figure 9-2. PLL Loop Filter Connections in RM.
PLL filter calculator is attached.
I hope it helps you.
Have a great day,
RadekS
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