Hi Nandu,
In the case of your routine, the problem may happen when OR/NF/FE/PF is set while RDRF flag is cleared.
Note from RM: OR flag may read back as set when RDRF flag is clear. This may happen if the following sequence of events occurs:
- After the first frame is received, read status register SCISR1 (returns RDRF set and OR flag clear);
- Receive second frame without reading the first frame in the data register (the second frame is not
received and OR flag is set);
- Read data register SCIDRL (returns first frame and clears RDRF flag in the status register);
- Read status register SCISR1 (returns RDRF clear and OR set).
Event 3 may be at exactly the same time as event 2 or any time after. When this happens, a dummy
SCIDRL read following event 4 will be required to clear the OR flag if further frames are to be received.
Please use rather something like:
void Serial_ISR(void)
{
volatile uCHAR temp = 0, dataReg = 0;
temp = SCI0SR1;
if( temp & SCI0SR1_RXDF_MASK )
{
dataReg = SCI0_DATA_REG;
MODBUS_Fun(dataReg);
}
if( temp & SCI0SR1_OR_MASK )
{
//…
}
//…
}
When bodies of these branches will be the same/similar, you may use combination for flag testing.
Example of S12G SCI ISR:
#pragma CODE_SEG NON_BANKED
interrupt 20 void SCI0_Isr(void)
{
unsigned char scicr2,scisr1;
scisr1 = SCI0SR1; // save status register actual status
scicr2 = SCI0CR2; // save control register actual status
//if receiver interrupt is enabled and corresponding interrupt flag is set
if((scicr2 & SCI0CR2_RIE_MASK) && ((scisr1 & (SCI0SR1_OR_MASK | SCI0SR1_RDRF_MASK))))
{
if(scisr1 & SCI0SR1_OR_MASK) // if overrun error do nothing/something
{
(void)SCI0DRL; // clear interrupt flag
// do something
}
else
{
sc0_data_in = SCI0DRL; // read received character + clear interrupt flag
//do something with received data
}
}
}
#pragma CODE_SEG DEFAULT
I hope it helps you.
Have a great day,
Radek
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