Wondering if the recommended stabilization Capacitor can be reduced (minimum 4.7uF is recommended). My application using S12ZVL32 is running at 25MHz with internal oscillator, without external ballast transistor and an external load of around 20mA max. Application uses LIN Phy (+SCI), ADC, RTI, API, HVI and Timers. I am already using a 1uF ceramic capacitor across Vdda and Vddx pins, so around 2uF near the MCU.
Thanks. Please note this application has to comply with ISO26262 ASIL A and whatever value we select must be either recommended in the datasheet or need to be justified by a calculation (if we select other). There must be some calculation from the designer of the regulator to have selected a 4.7uF capacitor. We need precisely that calculations so that we can justify in writing the value we select.
Please check with the designer.
I discussed this issue with another team but I didn’t obtain any calculation that could validate your changes. The conclusion is that the value is given and you should follow the datasheet.
Unfortunately, I haven’t got any specks regarding this capacitor. The value 4.7uF is given. But if your application doesn’t stress the power supply so much, you measured it and it is stable, in my opinion, it can be reduced.