S12ZVL: how to sync ADC with PWM rising edge

[keli]

Hi, there,

I am using S12ZVL to control a brushed DC motor. I would like to read bus current (through ADC) after the rising edge of the PWM. Any suggestion. Sample code will be appreciated.

Thanks, Ke

[RadekS]

Hi Ke,

You could use ETRIG0 input as Trigger Event signal.

See example code in attachment.

I hope it helps you.

Have a great day,
RadekS

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[kelimagna]

Hi, Radek,

Thanks for the code. I am using 32 QFN, which doesn't have PP6. I am thinking to config PAD5 as input and direct-connect it with PP1 (my PWM pin). My concern is the PWM signal slope. Does it make sense?

Thanks, Ke

[RadekS]

Hi Ke,

In that case, external connection is probably best way.

PWM signal slope will depend on load which you connect to PP1 pin. Simple connection to PAD5 should have minimal impact.

If you will use PAD5, please enable digital input buffer by DIEN_DIENAD5 bit.

Optionally you could enable port P interrupt and triggering ADC by “ADC0FLWCTL_TRIG = 1;” command inside Port P interrupt routine. However this approach adds additional overhead for CPU and increase delay between PWM edge and ADC trigger event. Enter into interrupt routine takes some time (several bus clock cycles) and this time delay isn’t deterministic because CPU have to finish current instruction prior enter into interrupt routine.

On other side, solution with port interrupt allows to you drive time between PWM edge and ADC trigger event by software. Solution with ETRIG0 needs external circuit (or some additional routing to timer module) for driving time delay between PWM edge and ADC trigger event.

I hope it helps you.

Have a great day,
RadekS

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