Hi Phil,
What do you mean by 5 cycles, bus clock cycles/timer counter cycles? And what function of timer do you use? Also, you didn’t mention the S12Z derivative.
In general, when an interrupt is recognized, the CPU responds upon completion of the instruction that is currently being executed. So, the Interrupt latency varies according to the number of cycles required to complete the current instruction. See Chapter 8 Instruction Execution Timing of the CPUS12Z_RM.
Can you share a test project so I could test it both, from Flash and RAM?
Regards,
Daniel