Query regarding external oscillator frequency selection for PLL Configuration based on S12ZVC Evaluation board.

[bhushanpatil]

Hi,

I am using S1912ZVCA19F0WKH (magni v 192kB) controller.

In the VLG_MC9S12ZVC project demo code which we got along with Evaluation board.

The PLL configuration is as below.

//inits the pll

void PLL_init() {

CPMUCLKS_PLLSEL = 1; //FBUS = FPLL/2.   FBUS = 32MHz,

CPMUREFDIV_REFFRQ = 1; //Reference clock between 2MHZ and 6MHZ.   

CPMUREFDIV_REFDIV = 0x1; //FREF=8/(1+1) = 4MHZ

CPMUSYNR_VCOFRQ = 0x1; //FVCO is between 48MHZ and 80MHZ 

CPMUSYNR_SYNDIV = 0x7; //FVCO = 2xFREFx(SYNDIV+1)   =   FVCO = 2x4x(7+1) = 64MHZ

CPMUPOSTDIV_POSTDIV = 0x0; //FPLL = FVCO/(POSTDIV+1).  FPLL = 64MHZ/(0+1)    FPLL = 64MHz   

CPMUOSC_OSCE = 1; //External oscillator enable. 8MHZ. FREF=FOSC/(REFDIV+1)

while(!CPMUIFLG_LOCK){} // Wait for LOCK.

CPMUIFLG = 0xFF; // clear CMPMU int flags - not needed but good practice   

}

But the external oscillator used in evaluation board is of 4MHz.

I would like to know why external oscillator frequency(fosc) is considered as 8Mhz in the configuration for calculating Fref.

FREF=FOSC/(REFDIV+1): FREF=8/(1+1) = 4MHZ.

If I consider fosc = 4Mhz for calculating reference frequency based on formula I need to set REFDIV = 0 ; to achieve 4Mhz of reference frequency.

If I use REFDIV = 0 ,  PLL lock will not happen.

Please let me know on what basis fosc is considered as 8Mhz.

Regards,

Bhushan

[RadekS]

Hi Bhushan,

It seems that PLL code was overtaken from different board code.

As reference code for PLL you could use this source (with exception in case of GDUF register, which is not available at S12ZVC):

https://community.nxp.com/docs/DOC-330238

You could use also attached PLL calculator.

How to use: Please select S12P (it was first S12 MCU family with CPMU module), input clock frequency and requested bus clock. It will directly calculate optimal values of CPMUSYNR, CPMUREFDIV, and CPMUPOSTDIV registers.

Note: This calculator is older than newest S12Z derivatives, therefore the highest bus clock values are detected as non-valid (above 32MHz).

I hope it helps you.

Have a great day,
Radek

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