S12ZVM clock module and PLL configuration - SW examples

Document created by iggi Employee on Mar 24, 2016Last modified by Daniel Martynek on Feb 11, 2020
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In the attached zip file you can find three software examples demonstrating clock module and PLL configuration on MagniV device MC9S12ZVM.

The examples are made in CodeWarrior IDE v10.6 (Eclipse).

The main.c source file of each project provides detailed description, comments and important notes.


The source code can be used with other devices within MagniV family based on S12Z core such as S12ZVL, S12ZVC, S12ZVH/Y, but the precaution must be considered about the max bus frequency of the device.


p.s. Revision 2:

SYNR, REFDIV and POSTDIV values changed in PLL initialization to achieve highest PLL locking time.

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