Why the port pins PS0 and PJ0 are not getting driven High on S12ZVCA Evaluation board?

[bhushanpatil]

Hi,

I am using S12ZVC Evaluation Board.(S912ZVCA19F0WKH [magni v 192kB])

It has been observed that the port pins PS0 and PJ0 when configured as GPIO(Outputs) and forced to logic level HIGH

by writing to the respective Data Direction Register(DDRx) and Port Data Register(PTx) does not reflect into HIGH level on board.

Instead of both the pins (PS0 and PJ0) driven to 5 Volts the behavior observed was as mentioned below:

Physical Voltage on PS0 Pin -  3 Volts

Physical Voltage on PJ0 Pin - 0.1 Volts(Approx)

Guidance on the deviation of the results will be helpful !

Thanks & Regards,

Bhushan Patil

[RadekS]

Hi Bhushan,

From my point of view, it looks like some collision of two (or more) output signals.

The PS0 pin is internally connected to DOUT pin at MMA6900KQ IC on VLG-S12ZVC board.

Please check whether you disconnected J42 jumper for disabling MMA6900KQ power supply.

The PJ0 pin is internally connected to OSBDM interface (to virtual serial port). Do you use OSBDM on board interface for debugging?

Anyway, it is not a healthy situation and this might damage (part of) MCU.

The ports S and J have also PTIJ and PTIS register with values which refers to voltages at appropriate pins. The overcurrent/short could be simple detected by comparing PTJ and PTIJ (PTS and PTIS) registers.

I hope it helps you.

Have a great day,
Radek

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