Interrupt Queing

[Pinak]

For executing an important task, interrupts(gloabl) are disabled and enabled after the task has completed.

During this process(interrupts disabled), if interrupt occours, will that interrupt be served after interrupts are enabled again?

[kef]

Setting I bit in CPU status register disables interrupts servicing (calling interrupt handlers by CPU), but doesn't clear and doesn't prevent setting interrupt flags by hardware. Interrupts, whose flags are set, will be serviced after you clear I bit.

Your important task should take as short as possible. For example in case of SCI interrupts, I bit = 1 should take less than it is required to send 2 bytes over SCI at given baud rate, else you may loose data.

[Pinak]

Hello Edward,

Thanks for the reply. Your reply cleared my doubts.

If I understood correctly, you mean to say it is programmers responsibility to take care to complete the task within stipulated time, as mentioned below for SCI.

But here we have taken an example of only  SCI interrupt. In case more than one interrupts are used, then how interrupts would be serviced?

For ex. In addition to SCI, two more interrupts are used in system. When interrupt are disabled, remaining both the interrupts occur, will both interrupts be serviced depending upon their priority after enabling the interrupts again?

Your reply will be helpful.

[kef]

It is programmers responsibility to keep interrupts disabled for no more time than it takes to set given interrupt flag twice. In case you have 10 interrupt sources to handle, you need to provide that each of these interrupt events can't occur more than once while interrupts are disabled, else you will certainly loose some interrupt events.

[RadekS]

Yes, correct.

When you clear I-bit, first will be serviced interrupt with higher priority.

For example:

Basic priority is given by interrupt address. If two or more interrupt requests are received concurrently, the request with the highest address (closest to $FFFF) is serviced first (valid for I-bit maskable interrupts).

At S12XD you can set interrupt priority levels by INT_CFADDR and INT_CFDATAx registers (seven priority levels).

If you are looking for software solution with interrupt nesting (interrupt routine is interrupted by interrupt with higher priority) at older S12 MCUs, I would like recommend our application note AN2617 A Software Piority Interrupt Scheme on HCS12 Microcontrollers:

http://www.freescale.com/files/microcontrollers/doc/app_note/AN2617.pdf

http://www.freescale.com/webapp/sps/download/license.jsp?colCode=AN2617SW

[Pinak]

Thanks Radek for the reply.