I am sorry I am not able to answer. I am not sure I have missed something but we have to think about different clocks:
1) BUSCLK frequency of the bus.
What value of BUSCLK you want to have?
2) OSCCLK frequency of the oscillator from which the busclk is derived. (12MHz in your case)
3) CANCLK - frequency of input clocks to a CAN module. The CANCLK can be OSCCLK or BUSCLK.
If the CANCLK is derived directly from OSCCLK the busclk does not influence CANCLK.
The results are highlighted. The only problem I see sample point. If it suits to you then it is OK.
I can see you use ATD and SCI in your example without any info about busclk from which the clock for these peripherals are derived. I have look at your SCI setup and you really use 6.25MHz busclk.
Now there are two ways:
1) Either select new busclk and adjust clock setup for SCI and ATD
2) or to use original clock setup for ATD and SCI peripherals and try to trim busclk to 6.25MHz.
If I assume item 2, then your original setup is OK and I suppose you do not want to change anything in the ATD and SCI peripheral setup, so:
| OSC[MHz] | SYNDIV | VCOFRQ | REFDIV | REFFRQ | POSTDIV | fref | fvco | fPLL | fvco/fref | fbus |
| 12 | 24 | 1 | 11 | 0 | 3 | 1 | 50 | 12.5 | 50 | 6.25 |
// make 6.25MHz BUSCLK from the external oscillator 12MHz
void CPMU_Init( void )
{
//============================================================================
ECLKCTL_NECLK = 0; //enable ECLK (BUSCLK at PP0)
//============================================================================
//Default state after reset:
// So after reset:
// CPMUOSC_OSCE == 0 => fref = firc1m = 1MHz
// CMPU_PLLSEL == 1 => fpll = fref / 4 = while not locked
// = 1MHz / 4 = 250kHz
// then fpll = 2 * fref *(syndiv+1) / (postdiv + 1) =
// = 2 * 1MHz *(24 +1) / (3 + 1) =
// = 50 / 4 = 12.5MHz
// fbus = fpll / 6.25MHz
Delay( 1000 ); //delay in order to see default bus frequency on ECLK output
//============================================================================
// PLL setup 16 MHz BUSCLK from 4 MHz
// expected frequency after lose of OSC, PEE, PBE:
// - fbus= fpll/2= 1/4MHz/2 = 125 kHz till locked then
// - fbus= fpll/2= 2*fref*(syndiv+1)/(postdiv + 1)/2 = 2*1*25/(3+1)/2=6.25MHz
CPMUSYNR = 0x58; // 0B01_0x18
CPMUREFDIV = 0x0B; // 0B00_0x0B
CPMUPOSTDIV = 0x03;
CPMUOSC_OSCE = 1;
while( CPMUIFLG_UPOSC == 0 )
{
__RESET_WATCHDOG(); // if COP is enabled by HW then it should be served in loops
// add some code for time out error
}
// PLLSEL - CPMUCLKS_PLLSEL = 1; // PEE ; CPMUCLKS_PLLSEL = 0; // PBE
// PSTP - COP stopped in STOP mode
// CSAD - COP stopped in STOP mode
// COPOSCSEL1 = 0; COP clock derived by COPOSCSEL0
// PRE - RTI disabled when pseudo STOP
// PCE - COP stopped in pseudo STOP mode
// RTIOSCSEL - RTI clock source is IRCCLK
// COPOSCSEL0 = 0; COP clock source IRCCLK
// After writing CPMUCLKS register, it is strongly recommended to read
// back CPMUCLKS register to make sure that write of PLLSEL,
// RTIOSCSEL and COPOSCSEL was successful. This is because under
// certain circumstances writes have no effect or bits are automatically
// changed
// You can add some timeout into the loop if required
do
{
//CPMUCLKS = 0B10100000;
CPMUCLKS = 0B10000000;
// add some code for time out error
}
// while( CPMUCLKS != 0B10100000);
while( CPMUCLKS != 0B10000000);
#ifdef COP_EXAMPLE
CPMUCOP = 0B01000101; //4.194304s till timeout, 1MHz IRCCLK used by default
//RSBCK == 1; COP and RTI Stop in Active BDM Mode Bit
#endif
// voltage regulator selections
// select power option
//.........................................
//Note: Write once Register
//CPMUVREGCTL = 0x06; //Turn on Ballast transistor for VDDX domain
//and switch on regulator for VDDC domain
//OR
CPMUVREGCTL = 0x05; //Internal voltage regulator for VDDX domain
//and switch on regulator for VDDC domain
}
Best regards,
Ladislav
Hi Ladislav,
Your code of CPMU_Init() (as following) can work fine for ADC & SCI. Thank you.
I wrote CAN_Init() & CANPHY_Init() as following. Do you have any recommendations ?
void CAN_init(void)
{
// initialise MSCAN
CAN0CTL0 = 0x01; // MSCAN in initialization mode
while (!(CAN0CTL1_INITAK)){} // Loop when Initialization mode inactive
CAN0CTL1_CANE = 1; // Enable MSCAN module
CAN0CTL1_CLKSRC = 0; // Clock source is OSCCLK = 12 MHz
CAN0CTL1_LOOPB = 0; // DISABLE LoopBack Mode
CAN0CTL1_LISTEN = 0; // Not listen only mode
CAN0CTL0_WUPE = 1; // Enable WAKEUP//Baud rate = CANCLK/(Pre-scaler * time quanta)
CAN0BTR0 = 0xC2; // SJW = 3 (4 Tq clock cycles), BRP = 2 (Baud Rate Prescaler = 3, CANCLK = 12MHz/3=4MHz)
CAN0BTR1 = 0xE7; // 3 Sample/bit, TSEG2=6 (Time Segment 2 = 7 Tq clock cycles), TSEG1=7 (Time Segment 1 = 8 Tq clock cycles)//accept all messages
CAN0IDAC_IDAM = 0; /* Two 32 bit filters */
CAN0IDMR0 = 0xFF; /* Accept all incoming ID's */
CAN0IDMR1 = 0xFF;
CAN0IDMR2 = 0xFF;
CAN0IDMR3 = 0xFF;
CAN0IDMR4 = 0xFF;
CAN0IDMR5 = 0xFF;
CAN0IDMR6 = 0xFF;
CAN0IDMR7 = 0xFF;
//exit initialization mode
CAN0CTL0_INITRQ = 0;
while (CAN0CTL1_INITAK){};
while(!(CAN0CTL0_SYNCH)){};
//clear flags
CAN0RFLG_RXF = 1;
CAN0RIER_RXFIE = 1;
}void CANPHY_init(void)
{
//enable physical layer
CP0CR_CPE = 1; // ENABLE CAN Physical
CP0CR_SLR = 4; // Slew Rate = 4 (Tx+Rx delay = 153ns)
CP0IE = 0; // DISABLE Interrupts
CP0CR_SPE = 1; // ENABLE SPLIT = 2.5V
CP0CR_WUPEI = 1; // Configure Wake-up (01: ENABLE wake-up receiver, 1st wake-up event is masked)
}
Best Regards,
Aaron
Hi Ladislav,
I only see 2 rows show "OK". What's wrong?
I will modify my code by following your reply later. Thank you.
Best Regards,
Aaron
Hi Ladislav,
My mistake. Thanks for your reply.
I select following parameter.
But my code(as attachment) can not sent any CAN-bus data. Please help.
Best Regard,
Aaron
Hi Ladislav,
I only know the parameter of marked (12, 250000 & 10).
I want to use CLKSRC=0 (MSCAN clock source is the oscillator clock) & internal physical interface in S12ZVC.
Best Regards,
Aaron
I am sorry I am not able to answer. I am not sure I have missed something but we have to think about different clocks:
1) BUSCLK frequency of the bus.
What value of BUSCLK you want to have?
2) OSCCLK frequency of the oscillator from which the busclk is derived. (12MHz in your case)
3) CANCLK - frequency of input clocks to a CAN module. The CANCLK can be OSCCLK or BUSCLK.
If the CANCLK is derived directly from OSCCLK the busclk does not influence CANCLK.
The results are highlighted. The only problem I see sample point. If it suits to you then it is OK.
I can see you use ATD and SCI in your example without any info about busclk from which the clock for these peripherals are derived. I have look at your SCI setup and you really use 6.25MHz busclk.
Now there are two ways:
1) Either select new busclk and adjust clock setup for SCI and ATD
2) or to use original clock setup for ATD and SCI peripherals and try to trim busclk to 6.25MHz.
If I assume item 2, then your original setup is OK and I suppose you do not want to change anything in the ATD and SCI peripheral setup, so:
| OSC[MHz] | SYNDIV | VCOFRQ | REFDIV | REFFRQ | POSTDIV | fref | fvco | fPLL | fvco/fref | fbus |
| 12 | 24 | 1 | 11 | 0 | 3 | 1 | 50 | 12.5 | 50 | 6.25 |
// make 6.25MHz BUSCLK from the external oscillator 12MHz
void CPMU_Init( void )
{
//============================================================================
ECLKCTL_NECLK = 0; //enable ECLK (BUSCLK at PP0)
//============================================================================
//Default state after reset:
// So after reset:
// CPMUOSC_OSCE == 0 => fref = firc1m = 1MHz
// CMPU_PLLSEL == 1 => fpll = fref / 4 = while not locked
// = 1MHz / 4 = 250kHz
// then fpll = 2 * fref *(syndiv+1) / (postdiv + 1) =
// = 2 * 1MHz *(24 +1) / (3 + 1) =
// = 50 / 4 = 12.5MHz
// fbus = fpll / 6.25MHz
Delay( 1000 ); //delay in order to see default bus frequency on ECLK output
//============================================================================
// PLL setup 16 MHz BUSCLK from 4 MHz
// expected frequency after lose of OSC, PEE, PBE:
// - fbus= fpll/2= 1/4MHz/2 = 125 kHz till locked then
// - fbus= fpll/2= 2*fref*(syndiv+1)/(postdiv + 1)/2 = 2*1*25/(3+1)/2=6.25MHz
CPMUSYNR = 0x58; // 0B01_0x18
CPMUREFDIV = 0x0B; // 0B00_0x0B
CPMUPOSTDIV = 0x03;
CPMUOSC_OSCE = 1;
while( CPMUIFLG_UPOSC == 0 )
{
__RESET_WATCHDOG(); // if COP is enabled by HW then it should be served in loops
// add some code for time out error
}
// PLLSEL - CPMUCLKS_PLLSEL = 1; // PEE ; CPMUCLKS_PLLSEL = 0; // PBE
// PSTP - COP stopped in STOP mode
// CSAD - COP stopped in STOP mode
// COPOSCSEL1 = 0; COP clock derived by COPOSCSEL0
// PRE - RTI disabled when pseudo STOP
// PCE - COP stopped in pseudo STOP mode
// RTIOSCSEL - RTI clock source is IRCCLK
// COPOSCSEL0 = 0; COP clock source IRCCLK
// After writing CPMUCLKS register, it is strongly recommended to read
// back CPMUCLKS register to make sure that write of PLLSEL,
// RTIOSCSEL and COPOSCSEL was successful. This is because under
// certain circumstances writes have no effect or bits are automatically
// changed
// You can add some timeout into the loop if required
do
{
//CPMUCLKS = 0B10100000;
CPMUCLKS = 0B10000000;
// add some code for time out error
}
// while( CPMUCLKS != 0B10100000);
while( CPMUCLKS != 0B10000000);
#ifdef COP_EXAMPLE
CPMUCOP = 0B01000101; //4.194304s till timeout, 1MHz IRCCLK used by default
//RSBCK == 1; COP and RTI Stop in Active BDM Mode Bit
#endif
// voltage regulator selections
// select power option
//.........................................
//Note: Write once Register
//CPMUVREGCTL = 0x06; //Turn on Ballast transistor for VDDX domain
//and switch on regulator for VDDC domain
//OR
CPMUVREGCTL = 0x05; //Internal voltage regulator for VDDX domain
//and switch on regulator for VDDC domain
}
Best regards,
Ladislav
