Hi
What could be wrong:
1) You use canned oscillator (external clock) with wrong output voltage. It must have Vddpll value of 1.8V. If it is larger the divider must be used.
Check the design with:
https://community.nxp.com/t5/S12-MagniV-Microcontrollers/Reference-schematics-for-S12-X-devices/ta-p...
This is ticking time bomb because of electromigration in oscillator circuitry.
2) Maximum oscillator value is defined in the Table A-24
a) Crystal oscillator range (loop controlled Pierce) fOSC 4.0 — 16 MHz
b) Full swing Pierce oscillator/external clock mode is selected fOSC 2.0 — 40 MHz
3) Incorrect order in PLL initialization. Refdv (divider) must be set earlier than Synr (multiplier).
void PLL_setup(unsigned char _synr, unsigned char _refdv, unsigned char _postdiv)
{
PLLCTL = 0B00000001; // CME=0,PLLON=0,FM1=0,FM2=0,FSTWKP=0,PRE=0,PCE=0,SCME=1
CLKSEL = 0B00000011; // PLLSEL=0,PSTP=0,PLLWAI=0,RTIWAI=1,COPWAI=1
REFDV = _refdv; // Set the divider register
SYNR = _synr; // Set the multiplier register
POSTDIV = _postdiv; // Set the post divider register
PLLCTL_PLLON = 1; // Enable the Phase Lock Loop
while(!CRGFLG_LOCK); // Wait till the PLL VCO is within tolerance
CLKSEL_PLLSEL = 1; // Select clock source from PLLCLK
// optional to be able to check correct bus clock
ECLKCTL_NECLK=0; // Enable the BusClk output at ECLK pin to see busclk if necessary
}
4) Incorrect design of oscillator circuitry and load capacitors.
(no wire, no plain under oscillator circuitry is allowed..it changes capacitance)
5) Incorrect registers calculation. Use calculator
https://www.nxp.com/docs/en/user-guide/S12XEIPLLCUG.pdf
https://www.nxp.com/downloads/en/calculators/S12XESW.zip
Best regards,
Ladislav