GDU VLS threshold

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GDU VLS threshold

Contributor V

Hello All,

I am using ZVML64 with GDUV4. From the RM v2.13, the voltage thresholds for undervoltage on VLS for GDU V4 are VLVLSHA and VLVLSHD.

Under the GDUF register description , for GLVLSF bit , for bit value 0 ->VLS_OUT pin voltage is above VLVLSD

Question 1) My understanding is that VLVLSD is nothing but VLVLSHD. It is an prinitng error. Can anyone please confirm the same.?

Question 2) After having a quick look at the GDU electrical characteristics table for V4 for VLVLSHA and VLVLSHD [10a and 10b respectively], I can see that the min,typ and max voltage levels are almost overlapping if not equal.

My thinking is that; due to these overlapping thresholds, the GLVLSF bit will set immediately once it is cleared or viceversa [if the voltages are at that detection level]

Can someone please explain if these overlapping levels are ok and reason for the overlapping voltage levels.

Thank you

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NXP TechSupport
NXP TechSupport

Hello pratibhasurabhi,

Yes, there should be:
0 = VLS_OUT pin voltage is above VLVLSHD or VLVLSLD

There is a hysteresis although it is not specified.
You can see that the typical deassert level is a bit higher than the assert level.
So, it should not flag the error immediately, the VLS_OUT voltage would need to drop.