Which exception level U-boot executes in LS1046A

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Which exception level U-boot executes in LS1046A

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vijaykumardesai
Contributor II

When I get a control into my bare metal code after bootm it is already in EL2.

I wanted to if Uboot executes in EL2 and it executes in EL3 and drops down to EL2 while leaving?

What should I do to let Uboot leave in EL3?

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Vijaykumar Desai,

1. Bootcore branches to 1st stage bootloader running in EL3
2. Bootcore in 1st stage bootloader branches to EL3 init code in PPA
3. When bootcore completes EL3 init, it branches to 2nd stage bootloader in EL2
4. Bootcore in 2nd stage bootloader branches to Linux kernel in EL1

You could refer to the following procedure to switch from EL3 to EL2 for ARMv8.

/*
 * Switch from EL3 to EL2 for ARMv8
 * @ep:     kernel entry point
 * @flag:   The execution state flag for lower exception
 *          level, ES_TO_AARCH64 or ES_TO_AARCH32
 * @tmp:    temporary register
 *
 * For loading 32-bit OS, x1 is machine nr and x2 is ftaddr.
 * For loading 64-bit OS, x0 is physical address to the FDT blob.
 * They will be passed to the guest.
 */
.macro armv8_switch_to_el2_m, ep, flag, tmp
        msr     cptr_el3, xzr           /* Disable coprocessor traps to EL3 */
        mov     \tmp, #CPTR_EL2_RES1
        msr     cptr_el2, \tmp          /* Disable coprocessor traps to EL2 */

        /* Initialize Generic Timers */
        msr     cntvoff_el2, xzr

        /* Initialize SCTLR_EL2
         *
         * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
         * and RES0 bits (31,30,27,26,24,21,20,17,15-13,10-6) +
         * EE,WXN,I,SA,C,A,M to 0
         */
        ldr     \tmp, =(SCTLR_EL2_RES1 | SCTLR_EL2_EE_LE |\

                        SCTLR_EL2_WXN_DIS | SCTLR_EL2_ICACHE_DIS |\
                        SCTLR_EL2_SA_DIS | SCTLR_EL2_DCACHE_DIS |\
                        SCTLR_EL2_ALIGN_DIS | SCTLR_EL2_MMU_DIS)
        msr     sctlr_el2, \tmp

        mov     \tmp, sp
        msr     sp_el2, \tmp            /* Migrate SP */
        mrs     \tmp, vbar_el3
        msr     vbar_el2, \tmp          /* Migrate VBAR */

        /* Check switch to AArch64 EL2 or AArch32 Hypervisor mode */
        cmp     \flag, #ES_TO_AARCH32
        b.eq    1f

        /*
         * The next lower exception level is AArch64, 64bit EL2 | HCE |
         * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
         */
        ldr     \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
                        SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
                        SCR_EL3_NS_EN)
        msr     scr_el3, \tmp

        /* Return to the EL2_SP2 mode from EL3 */
        ldr     \tmp, =(SPSR_EL_DEBUG_MASK | SPSR_EL_SERR_MASK |\
                        SPSR_EL_IRQ_MASK | SPSR_EL_FIQ_MASK |\
                        SPSR_EL_M_AARCH64 | SPSR_EL_M_EL2H)
        msr     spsr_el3, \tmp
        msr     elr_el3, \ep

        eret


Have a great day,
TIC

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