Using CPC as SRAM

[yipingwang]

Hello Hymalai,

You could use "Download" when create the bare board project, the debug program will be download at the effective address 0, so downloading program to DDR or SRAM depends on what kind of memory is mapped to effective address 0 in the initialization file.

Have a great day,
Yiping

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[hymalaibello]

Hi!

Hello Hymalai,

You could use "Download" when create the bare board project, the debug program will be download at the effective address 0, so downloading program to DDR or SRAM depends on what kind of memory is mapped to effective address 0 in the initialization file.

Have a great day,
Yiping

When I try to do that,  the program do not debug. and SRAM is mapped to effective address 0 using law, and DDRs are disabled.

Thanks!

Regards,

Hymalai Bello

[yipingwang]

Hello Hymalai,

In the default RAM lcf file P4080DS_gcc-eabi_core0.lcf, the stack and heap definitions are out of the range of 1M CPC as SRAM, and the TLB miss exception will be encountered. Please use SRAM version LCF file  e500mc_gcc-eabi_SRAM.lcf, which I mentioned in the previous thread.

Have a great day,
Yiping

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[hymalaibello]

Hi!

Can I use the registers for  Partition allocation of CPC (CPC1_CPCPAR1....) when I am using CPC as SRAM?  Is for assign  a private space to each core.

thanks!

Regards,

Hymalai Bello

[yipingwang]

Hello Hymalai,

The L3 CPC can be configured as:

SRAM

Unified, I-only, D-only

Locking (per Line)

I/O Stashing

Allocating logical Partition is needed  if the L3 CPC block is configured for I/O Stashing.

If you would like to close this thread and discuss this topic in a new thread, please help to mark useful answers of this thread, thanks.

Thanks,

Yiping