Questions about T1042 processor and U-boot

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Questions about T1042 processor and U-boot

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yusufalti333
Contributor IV

We have a custom board based on t1042 processor. Using codewarrior rcw override option, We successfully wrote RCW, FMan Ucode and U-boot in given flash locations in SDK V2.0 - 1703 ( Current Bank adresses ).

When I power up the board again, I do not see any output from serial port. I was expecting at least seeing U-boot <version> <compile date> and CPU information at the console output yet I observe no activity at all. I am using default u-boot compiled with SDK V2.0 -1703 version.

Can you please guide me for alternative methods?  How can I be sure where is the problem ?

Thanks.

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ufedor
NXP TechSupport
NXP TechSupport

3) Use a digital scope to check behaviour of the reset signals shown in the QorIQ T1040 Reference Manual, Figure 4-1. Power-on reset sequence

Please describe behaviour of all signals after PORESET_B is deasserted (low -> high).

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ufedor
NXP TechSupport
NXP TechSupport

Please use a digital scope and check RCW_SRC[0:8] behaviour at PORESET_B deassertion edge (low->high).

Ensure that the PORESET_B edge rise/fall time is not more than 1 SYSCLK.

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ufedor
NXP TechSupport
NXP TechSupport

1) Please provide the RCW binary image for inspection.

2) Use a digital scope to ensure that RCW is read from the NOR Flash after PORESET_B is deasserted - i.e. that cfg_rcw_src signals have correct levels when PORESET_B is asserted.

3) Use a digital scope to check behaviour of the reset signals shown in the QorIQ T1040 Reference Manual, Figure 4-1. Power-on reset sequence.

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yusufalti333
Contributor IV

For 2-3,

Without using digital scope, we have ensured that;

Before PORESET_B is asserted, cfg_rcw_src is set for NOR flash and right after it PORESET_B is asserted (logic high to low) by system logic and kept for 2 ms. During that time, it is also observed that CPU asserts HRESET_B. And then after PORESET_B is deasserted (logic low to high), cfg_rcw_src [0:8] (IFC_AD8-15 & IFC_CLE) pins are released and 'Z' is driven by system logic.

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ufedor
NXP TechSupport
NXP TechSupport

3) Use a digital scope to check behaviour of the reset signals shown in the QorIQ T1040 Reference Manual, Figure 4-1. Power-on reset sequence

Please describe behaviour of all signals after PORESET_B is deasserted (low -> high).

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yusufalti333
Contributor IV

Hello ufedor

While debugging, we confirmed that RCW_SRC[0:8] is always changing randomly, as shown in the screen captures ( Capture 2,4 and 5  .png files) I attached. 

In debug mode, u boot also loads a different rcw and Vbank is selected as 7 ( Please see Pbl Hexdump.png and u-boot-in-debug-mode.png files I attached).

We can make U-boot working until some point in debug mode (using RCW override method), but still no output in normal reset without Code Warrior.

Do you have any suggestion about this situation ? 

Thanks.

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yusufalti333
Contributor IV

Hello ufedor,

We confirmed that though we pull the pins to the high-Z position, it is not driven. We are working on it now.

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yusufalti333
Contributor IV

Hello ufedor,

We do not have a physical PORESET_B pin. We have Iglo(fpga) which is responsible of assertion and deassertion of PORESET_B. It seems quite impossible to measure reset signals with scope. 

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yusufalti333
Contributor IV

Hello ufedor,

I attached PBL.bin file (created with QCSV - code warrior) and RCW override file.

We'll see the values using scope, thanks.

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