P2041 e500mc MCSR[LDG] error without [LD], No Errors Found

[mehmetcelik]

Hi there,

I have a question regarding to getting details about 'LDG (Guarded Load Instruction)'
error reporting.

First of all we are using P2041 as the processor and according to
'E500MC Core Reference Manual, Rev. 3' document, Machine Check Syndrome Register (MCSR) has
a field named 'LDG'.

We receive the LDG bit of MCSR without the LD bit set and we couldn't identify the error. Set only if the error encountered by the load was an L2 or CoreNet error.` So if LDG field is set without the LD then that means we have error related to L2 or CoreNet. Therefore, when we saw the LDG field is set, we read the following registers to identify where the issue is.

For the CoreNet Part:
- CCF_CEDR
- CPC_CPCERRDET
- CPC_CPCCAPTECC
- CPC_CPCERRATTR
- CPC_CPCERRADDR
- CPC_CPCERREADDR
- CPC_CPCCAPTDATALO
- CPC_CPCCAPTDATAHI

For the L2 Part:
- L2ERRDET
- L2ERRATTR
- L2ERRADDR
- L2CAPTDATALO
- L2CAPTDATAHI

Other registers:
- MCAR
- MCARU
- MCSRR0

But according to our readings, those registers do not indicating any error. They are all clear.
So the question is are we missing any register that could help us to find the issue?

We are using 'QorIQ P2040 Reference Manual, Rev.4' as a reference for the CoreNet registers.

Thank you,

[mehmetcelik]

Thank you Alexander, that seems to be the issue here.

Cheers,

[alexander_yakov · Accepted solution]

Do you get this MCSR[LDG] when Error Report Machine Check Interrupt occurs? Or you see this bit set, but no Error Report Machine Check Interrupt reported? We have errata A-004770 stating that MCSR[LDG] may be set when asynchronous interrupt is taken.  

Have a great day,
Alexander,
TIC

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