LS1046A - SGMII Interface

[matthej]

Hi,

I will be designing a board utilizing the LS1046A processor. I have a few questions:

1) We plan on connecting the LS1046A processor to an Xilinx Ultrascale FPGA and I am looking to use one of the SGMII interfaces (1GbE) for primary communications to/from the processor. Do I need any PHY device between the two devices or can I just connect the RXP,RXN, TXP,TXN directly to the FPGA?

2) For this SGMII interface, I see in the reference manual (LS1046ARM) that on p.136, it mentions that you do not need to provide a clock to the processor for this (only connect up for signals), but on p.1965, Table 31-4, shows using either a 100MHz or 125MHz clock for SGMII. So do I need an external clock for the SGMII interface?

3) Also I need to config my FPGA. Do you have a recommendation on which interface to use (what most people use)? Does the PCIe or IFC interface get used typically for FPGA configuration?

Thanks,

Matty

[matthej]

Thanks! So for my question #1. I am not quite sure if I should set up this interface (MAC-MAC) with SGMII or 1000Base-KX (or 1000Base-X). Not sure of if there is any benefit in doing this? Both devices (LS1046 and FPGA) will be on the same board.

Thanks!

[ufedor]

SGMII is intended to be used between MAC and PHY.

1000Base-KX has to be used in MAC-to-MAC connection.

[matthej]

Hi,

Can I use it in either 1000Base-X or 1000Base-KX mode?

KX is for backplanes and X is for optical. Does it really matter since I am on board?

[ufedor]

> KX is for backplanes

1000Base-KX is fixed speed (as 1000Base-X) but enables exchange of equalization information with the connected device

This is why KX is usually used for MAC-to-MAC connections.

Technically 1000Base-X is supported on LS1046.

Please refer to SGMII_IF_MODE(SGMII IF Mode Register) in LS1046 Reference Manual, it contains control bits to set the interface mode.

SGMII_IF_MODE[SGMII_EN]

SGMII Mode Enable. When set to '0' (Reset Value), the PCS operates in standard 1000Base-X Gigabit mode, when set to '1', the PCS operates in SGMII Mode.

[ufedor]

1) Direct MAC-to-MAC connection is possible.

2) External clock is not a part of the SGMII interface, but appropriate reference clock is need for a SerDes module implementing the SGMII.

3) It is up to the board designer which interface to use for initial FPGA configuration. Also the implementation could depend on the specific FPGA requirements.

[matthej]

Sorry! Last question (thanks by the way, this has been helpful)

As I mentioned earlier, I need to configure three Xilinx FPGAs using the 1046A processor and I am looking at using the SPI interface to do this.

1) Does NXP have any reference designs that show the Processor configuring an FPGA?

2) Have you seen successful designs that use the SPI interface to do this?

I looked through all of the interfaces for the LS1046A and it looks like the SPI makes the most sense (although maybe I am overlooking something).

Thanks!

[kristof_tunner]

Dear matthej,

We have a design on which we are configuring an ultrascale fpga through the I2C interface of the ls1046a processor and this works well.

[matthej]

Hi Kristof,

I looked at the I2C interface but couldn't figure out a good way to get it to work. My questions are:

1) How did you handle the address phase of the transfer (just ignore it?)

2) Don't you need to ACK the master (LS1046A processor)? How did you do that?

3) How many FPGAs did you have to configure using this bus?

Thanks!

[ufedor]

1-2) No.