LS1046A PBI

[tian_shuliang]

File:packages\firmware\rcw\ls1046afrwy\NN_NNQNNPNP_3040_0506\rcw_1600_qspiboot.rcw

I don't understand the meaning of the following code, whether there are relevant manuals?

.pbi
// QSPI flash clock
write 0x57015c, 0x20100000 // set value  0x57015c to 0x20100000?
write 0x570600, 0x00000000
write 0x570604, 0x40100000
.end

.pbi
// QSPI END_CFG 64 bit LE
write 0x550000, 0x000f400c
.end

[yipingwang · Accepted solution]

Hello salmon tian,

Please refer to QSPI CONFIG Register (SCFG_QSPI_CFG) in LS1046 reference manual, the PBI command "write 0x57015c, 0x20100000" sets CLK_SEL for QSPI CONFIG Register, please refer to the following description.

0–3  CLK_SEL
These bits control the division of CGA1/CGA2 PLL clock to generate QuadSPI interface clocks.
0000 Divide by 256
0001 Divide by 64 (default)
0010 Divide by 32

PBI command "write 0x570600, 0x00000000" is used to configure SCFG_SCRATCHRW1(Scratch Read Write Registers) as 0.

PBI command "write 0x570604, 0x40100000" is used to configure SCFG_SCRATCHRW2 as 0x40100000.

SCRATCHRW1 - Reserved for future use in case boot location pointer is 64 bit. The value must be 0.
SCRATCHRW2 - 32-bit boot location pointer (BOOTLOCPTR)

The PBI command "write 0x550000, 0x000f400c" configures QuadSPI_MCR[END_CFG] as 64 bit LE, please refer to the section "26.8 Byte Ordering - Endianness" in LS1046 reference manual for details.

Thanks,

Yiping