SSI_LDD clock bug

[bowerymarc]

Setting the "Master Clock" to "Input Pin" in SSI_LDD results in this code in Audio0_Init (default name):

  /* I2S0_MCR: MOE=0 */

  I2S0_MCR &= (uint32_t)~(uint32_t)(I2S_MCR_MOE_MASK); /* Disable MCLK divider */

  while ((I2S0_MCR & I2S_MCR_MOE_MASK) != 0U) {} /* Wait for MCLK disable*/

  /* I2S0_MDR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FRACT=0,DIVIDE=0xF9 */

  I2S0_MDR = (I2S_MDR_FRACT(0x00) | I2S_MDR_DIVIDE(0xF9)); /* Configure Mclk divide ratio */

  /* I2S0_MCR: DUF=0,MOE=1,??=0,??=0,??=0,??=0,MICS=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */

  I2S0_MCR = (I2S_MCR_MOE_MASK | I2S_MCR_MICS(0x00)); /* Configure Mclk source */

Last line: MOE is set, making the MCLK line an output.

[vfilip · Accepted solution]

Hello,

thanks for reporting this bug to us. We will fix it for next release (I am not sure about CW V10.6 because we are close to this release. However this fix is going to be part of DriverSuite 10.4).

Best regards

Vojtech Filip

Processor Expert Support Team

[bowerymarc]

any workaround?

[vfilip]

Hello,

sorry I have omitted that. I think there are two possible ways how to workaround it. Either freeze generated code of this component by right click on component and use "Dont Write...." menu command or write the correct value into I2S0_MCR just after calling initialization method.

I2S0_MCR = I2S_MCR_MICS(0x00);       /* Configure Mclk source */

Best regards

Vojtech Filip

Processor Expert Support Team