LS1043 PCI-Ex Completion Timeout

[sahinduran]

Greetings all!

I was investigating the completion timeout behavior on PCI-EX. I tried to change the completion timeout interval via following steps below:

1- Removed the link on the corresponding lane. (No device is attached, no link present).

2- Configured the iATUs to issue config and memory transactions.

3- Programmed the Device Control 2 Register with appropriate various combinations.

4- Enabled the advanced error capture capabilities.

I observed the following results:

1- Single "load" instruction from configuration or memory space of the PEX took 50ms to complete, which stated as the default timeout of PCI-EX 3 base specification.

2- Completion timeout fail is reported via root error register and advanced error status register. (as expected)

No matter what values I wrote to Device Control 2 Register, completion timeout did not change.

I utilized PMC of Cortex A53 to measure elapsed time. I used different measurement means, yet the result is same. 

Is this the correct behavior or are we missing something?

Thanks is advance!

[yipingwang]

Please try modifying the timeout interval after the link is up with the PCIe device and repeat the same experiment. It might be switching to the default timeout interval after the link is up.