InterruptVector component

[leccy]

CW10.1

Kinetis K20

I would like to add an interrupt vector to my code, where the vector table is created by other PE components, but the InterruptVector component is currently disabled for my configuration.

Does anyone know when this will be resolved, or suggest a work-around in the mean time?

I am trying to emulate the code produced by PE for the RTC_LDD, but I am unhappy at how PE injects initialisation code into __init_hardware(), which causes a CPU_OnHardFault() exception if there is no power at VBAT.  I would like to handle the possibility of VBAT being disabled without getting stuck via the exception in __init_hardware().

Cheers

leccy

[ProcessorExpert]

Hello,

we are sorry for the inconvenience. The InterruptVector compoennt for Kinetis and CFV1+ families would be published in CW V10.3

Could you please specify why the CPU_OnHardFault() event from CPU component is not sufficient for you? I think it should provide the same functionality as if the hardfault would be handled by InterruptVector component...

Could you also please provide more details about your use case? Would be for example for you sufficient to provide hot-fix for you that will allow you to disable generation of RTC init. code in CPU.c and after that move the original RTC code from CPU.c to the user code?

The RTC init code, that would be moved into user code after applying the patch and disabling its generaiton in CPU.c:

  /* SIM_SCGC6: RTC=1 */
  SIM_SCGC6 |= (uint32_t)0x20000000UL;
  if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
    /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
    RTC_CR &= (uint32_t)~0x3C00UL;
    /* RTC_CR: OSCE=1 */
    RTC_CR |= (uint32_t)0x0100UL;
    /* RTC_CR: CLKO=0 */
    RTC_CR &= (uint32_t)~0x0200UL;
  }

best regards
Vojtech Filip
Processor Expert Support Team

[leccy]

Hi Vojtech

Thanks for your reply.

I was hoping to be able to catch the hard fault interrupt on the fragment you mention, and set a user flag such that i can display an error message when the code runs on into the main loop.  This would inform the user that there was a problem with the coin cell backup, and the unit needed to be returned to us.

As it stands, if VBAT is not available, the hard fault interrupt returns control to PE code, over which I have no control, and continues to interrupt at the same place, so the unit does not finish __init_hardware() and does not switch on.

As you mention, I would ideally call the fragment in my own code, and use the flag to prevent further attempts at reading RTC_CR, thereby preventing further occurences of the interrupt.

Do you have an expected release date for CW10.3?

Thanks

leccy

[ProcessorExpert]

Hello,

please find the attached hot-fix for the probelm. The hot-fix allows disabling generation of RTC inti. code in CPU.c.

Regaridng CW V10.3. I think that this release should be published in Q3 or Q4.

Note:

The steps how to apply the hot-fix are described in the readme in the zip archive.

best regards
Vojtech Filip
Processor Expert Support Team

[leccy]

Hi Vojtech

I did as instructed, and the patch did indeed disable the RTC oscillator in the CPU component.

Unfortunately, I get this error on compilation:
INTERNAL ERROR: Unexpected status of script: Beans\RTC_LDD\RTC_LDD.chg, please contact Freescale support.

I notice that you refer to CW10.2.  I am running CW10.1.  We are in a critical phase, and I have been reluctant to upgrade to CW10.2.

regards

leccy

[ProcessorExpert · Accepted solution]

Hello,

sorry for confusion. I have overlooked that you are using CW V10.1.

Please find attached the correct hot-fix for CW V10.1.

Before applying the new patch please do not forget to delete the files of the patch for 10.2.

PACKAGE_Patch05000501.pak.Index

PACKAGE_Patch05000501.pak

from {CodeWarrior}/MCU/ProcessorExpert/Beans

best regards
Vojtech Filip
Processor Expert Support Team

[leccy]

Many thanks!