CAN Receive Buffers on MKE06Z128VLH4

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CAN Receive Buffers on MKE06Z128VLH4

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samkreuze
Contributor II

Hello,

I'm developing an application on the MKE06Z128VLH4 which will use CAN for communication. In KDS I added the CAN_LDD component, configured it, and generated code. I am able to communicate via CAN using this module.  Now I would like to add another CAN RX Buffer to the component. In the Component Selector for CAN_LDD ->Settings->Message Buffers, I add a receive buffer but it will not allow it because it claims "CAN device supports only 1 receive buffer/s."  However, in the reference manual for this processor it claims "Five receive buffers with FIFO storage scheme"

I can add 3 transmit buffers to the component like the reference manual says.

Am I using the wrong component? or is this an issue with processor expert? or is there something I'm missing?

Thanks in advance,

Sam

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samkreuze
Contributor II

After digging into the reference manual further, I think I answered my own question.

Section 32.4.4 Receive structures:

"The received messages are stored in a five stage input FIFO. The five message buffers are

alternately mapped into a single memory area. The background receive buffer (RxBG) is

exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is

addressable by the CPU. This scheme simplifies the handler software because only one

address area is applicable for the receive process."

So, from what I can understand, when using the CAN_LDD you only have one receive buffer which is addressable and the component handles which message in the 5 buffers you access.

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1,439 次查看
samkreuze
Contributor II

After digging into the reference manual further, I think I answered my own question.

Section 32.4.4 Receive structures:

"The received messages are stored in a five stage input FIFO. The five message buffers are

alternately mapped into a single memory area. The background receive buffer (RxBG) is

exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is

addressable by the CPU. This scheme simplifies the handler software because only one

address area is applicable for the receive process."

So, from what I can understand, when using the CAN_LDD you only have one receive buffer which is addressable and the component handles which message in the 5 buffers you access.

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