After digging into the reference manual further, I think I answered my own question.
Section 32.4.4 Receive structures:
"The received messages are stored in a five stage input FIFO. The five message buffers are
alternately mapped into a single memory area. The background receive buffer (RxBG) is
exclusively associated with the MSCAN, but the foreground receive buffer (RxFG) is
addressable by the CPU. This scheme simplifies the handler software because only one
address area is applicable for the receive process."
So, from what I can understand, when using the CAN_LDD you only have one receive buffer which is addressable and the component handles which message in the 5 buffers you access.