why the pcie of MPC8315 can not detect the devices?

[linjiepan]

     Now,we are debugging MPC8315E chip based on the environment which is establish by the mirror of MPC8315ERDB_20100727_ltib.iso. In the uboot phase, when the PCIE is initialized,program will read “LTSSM State Status Register”，then return the value 0,which means "Detect quiet".Thus,it can't detect the PCIE device(BCM56134).

The L0 state of PCIE,is configure by hardware or software?IF it need configure,then how to configure?

in addition，the PCIE Bus address is assigned as follows:

/*

* General PCI

* Addresses are mapped 1-1.

*/

#define CONFIG_SYS_PCI_MEM_BASE   0x80000000

#define CONFIG_SYS_PCI_MEM_PHYS   CONFIG_SYS_PCI_MEM_BASE

#define CONFIG_SYS_PCI_MEM_SIZE     0x10000000 /* 256M */

#define CONFIG_SYS_PCI_MMIO_BASE  0x90000000

#define CONFIG_SYS_PCI_MMIO_PHYS  CONFIG_SYS_PCI_MMIO_BASE

#define CONFIG_SYS_PCI_MMIO_SIZE    0x10000000 /* 256M */

#define CONFIG_SYS_PCI_IO_BASE        0x00000000

#define CONFIG_SYS_PCI_IO_PHYS        0xE0300000

#define CONFIG_SYS_PCI_IO_SIZE          0x100000 /* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL 0x00000000

#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000

#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000

#define CONFIG_SYS_PCIE1_BASE              0x80000000

#define CONFIG_SYS_PCIE1_MEM_BASE    0x80000000

#define CONFIG_SYS_PCIE1_MEM_PHYS    0x80000000

#define CONFIG_SYS_PCIE1_MEM_SIZE      0x08000000 //128M

#define CONFIG_SYS_PCIE1_CFG_BASE    0x89000000

#define CONFIG_SYS_PCIE1_CFG_SIZE      0x01000000

#define CONFIG_SYS_PCIE1_IO_BASE        0x00000000

#define CONFIG_SYS_PCIE1_IO_PHYS        0x88000000

#define CONFIG_SYS_PCIE1_IO_SIZE          0x00010000

#define CONFIG_SYS_PCIE2_BASE              0xC0000000

#define CONFIG_SYS_PCIE2_MEM_BASE    0xC0000000

#define CONFIG_SYS_PCIE2_MEM_PHYS    0xC0000000

#define CONFIG_SYS_PCIE2_MEM_SIZE      0x02000000//0x10000000,改成32M

#define CONFIG_SYS_PCIE2_CFG_BASE    0xc2000000//0xD0000000

#define CONFIG_SYS_PCIE2_CFG_SIZE      0x01000000//16M

#define CONFIG_SYS_PCIE2_IO_BASE        0x00000000

#define CONFIG_SYS_PCIE2_IO_PHYS        0xC8000000//0xD1000000

#define CONFIG_SYS_PCIE2_IO_SIZE          0x00800000

#define CONFIG_PCI

#define CONFIG_83XX_GENERIC_PCI    1 /* Use generic PCI setup */

#define CONFIG_83XX_GENERIC_PCIE 1

#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES

thank you!

[r8070z]

>Do you mean that PCI Express controller can still detect a  PCIE receiver at any time

>when the PICE receiver is present on the PCIE bus ,after the PCI Express controller enter the internal LTSSM

Yes I mean.

The LTSSM is described in the PCIe specifications. I know the PCIe receiver input impedance is tested in order to detect it. So if the p1020 can detect the receiver you should pay attention to the MPC8315 board PCIe traces and A.C capacitors which are placed on the PCIe transmitter side. Also check the MPC8315 die revision The rev.1 may fail due to erratum I mentioned in the previous answer.

[linjiepan]

Now，I input “PCI 1” in SecureCRT , the print message is as follows:

Actually，On physical hardware，PCIe 1 connects with PCI device（BCM56134）.

When during scanning pci 1 bus,why It can't detect bcm56134?

In fact,Should be printed like this:

How to set the PCI configuration space, MEM space and  I/O space?

and Which register are need to set?

Such these Macro definitions,how to set ?

CONFIG_SYS_PCIE1_BASE、CONFIG_SYS_PCIE1_MEM_BASE、CONFIG_SYS_PCIE1_MEM_PHYS、CONFIG_SYS_PCIE1_MEM_SIZE?

CONFIG_SYS_PCIE1_CFG_BASE、CONFIG_SYS_PCIE1_CFG_SIZE?

CONFIG_SYS_PCIE1_IO_BASE、CONFIG_SYS_PCIE1_IO_PHYS、CONFIG_SYS_PCIE1_IO_SIZE?

thank you !

[linjiepan]

A.C capacitors are 0.1uf and board PCIe traces is similar with the p2020, so A.C capacitors and PCIe traces are not the problem

[linjiepan]

can you tell me the procedure of  PCIe initialization ?

MPC8314 still can not detect PCIE receiver？

[r8070z]

Have a great day,

The PCI Express link training algorithm is implemented in hardware. Following HRESET#, the PCI Express controller will enter the internal LTSSM (Link Training and Status State Machine), and may fail to properly detect a receiver as defined in the PCI Express Base Specification. Failing to properly detect a receiver can be determined by reading the LTSSM State Status Register. When this failure has occurred the status code can be either 0 or some other value. If the link has properly trained, the status code will read 0x16h.

There can be physical problem f.e. connection trace defect or improper capacitor. Also the MPC8315 rev.1 has erratum “PCI Express LTSSM may fail to properly train with a link partner” (Fixed in Rev 1.1 and later).

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[linjiepan]

Can PCI Express controller still detect a receiver if the receiver is not ready before the signal of  HRESET#?

[r8070z]

The PCI Express controller will enter the internal LTSSM following HRESET#.

[linjiepan]

On hardware,we did Cross test. when we push the P1020 core-plate On the button board which has pcie device(bcm56134), the p1020 can detect the bcm56134 by pcie bus.

But,when we push the MPC8315E core-plate on the same button board,the MPC8315E can not find the bcm56134.

The Information is printed as follows:

P1020：u-boot-2009.11;

MPC8315E：u-boot-2009.03-rc2;

In addition to the MEM_BASE、CFG_BASE、IO_BASE,which parameters need to be set。And how to  initialize the pcie??

thank you!

[linjiepan]

Do you mean that PCI Express controller can still detect a  PCIE receiver at any time when the PICE receiver is present on the PCIE bus ,after the PCI Express controller enter the internal LTSSM