Is this a bug in nand flash configuration of MPC8306SOM

[00lirui]

    I test mpc8306som board, and find a problem,the nor flash is S29GL064N90TFI03 ,the size is 8MB. the nand flash is 512MBytes MT29F4G08A. However the value of the BR and OR register is BR0= 0xfe001001 OR0 = 0xff800ff7  BR1= 0xfff00c21  OR1=0xfffc0796, I don't think the configuration is suitable.

    Another question,how to compile and  debug a application in codewarrior (windows) run in the RAM of board.

[scottwood]

It would be easier to answer your question if you'd explain why you think those values are wrong, whether you're talking about the NOR flash or the NAND flash, and where those values came from.

Also, please put separate questions in separate posts.

[scottwood]

OK, I see from the subject line that it's NAND you're concerned about.  The BR0 you posted is configured for GPCM, which wouldn't work with NAND at all.  It looks like it's configured for a 128 MiB NOR flash.

Did you boot from NAND?  If not, I don't think chipselect 0 is the one you should be looking at for NAND.

[00lirui]

The UBOOT boot from NOR FALSH, and the configuration of BR0 is correct. The BR1 control the NAND flash(LCS1), and the size of NAND is 512MByte,but you can't get it from the BR1 value (BR1= 0xfff00c21  OR1=0xfffc0796),That's the point confused me.

[yipingwang]

Hello Li Rui,

The following is the definition in CodeWarrior initialization file, which is similar as defined in u-boot header file.

# CS0 - 8MB NOR FLASH

writemem.l 0xe0005000 0xff801001 # BR0 base address at 0xff800000, port size 16 bit, GPCM, valid

writemem.l 0xe0005004 0xff806ff7 # OR0 8MB flash size, 15 w.s., timing relaxed

# CS1 - NAND Flash 32 KB

writemem.l 0xe0005008 0xf0000c21 # BR1 base address at 0xF0000000, port size 8 bit, FCM, valid

writemem.l 0xe000500c 0xFFFF8796 # OR1 32KB size

For BRn, ORn definition please refer to page 11-10(11) from http://cache.freescale.com/files/32bit/doc/ref_manual/MPC8306RM.pdf.

I think what you concern is OR1[AM], the following is its description.

GPCM address mask. Masks corresponding BRn bits. Masking address bits independently allows external

devices of different size address ranges to be used. Address mask bits can be set or cleared in any order in

the field, allowing a resource to reside in more than one area of the address map.

0 Corresponding address bits are masked and therefore don’t care for address checking.

1 Corresponding address bits are used in the comparison between base and transaction addresses.

Please note NAND Flash is IO device, unlike NOR Flash, it is not memory mapped device, only the SRAM within NAND Flash is mapped into memory, so the size is 32k, and ORn[AM] is 0xFFFF8000, this is correct.

Have a great day,
Yiping

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[00lirui]

Hi,

     Now I understand your mean. But  I want to test the NAND flash,  What should  I do? try some uboot commands? or other ways?

     Many thanks.

[yipingwang · Accepted solution]

Hello Li Rui,

You could verify NAND Flash read, write and erase functions under u-boot prompt(boot from NOR).

Please refer to the following methods provided in SDK document.

1. Boot the u-boot with NAND Flash driver enabled. Check

this in boot log,

NAND: * MiB

Where * is NAND flash size

2. Erase NAND Flash

3. Make test pattern on memory e.g. DDR

4. Write test pattern on NAND Flash

5. Read the test pattern from NAND Flash to memory e.g DDR

6. Compare the test pattern data to verify functionality.

/* U-boot prompt */

=> nand erase.chip

=> mw.b 1000000 0xa5 100000

=> md 1000000

01000000: a5a5a5a5 a5a5a5a5 a5a5a5a5 a5a5a5a5 ................

01000010: a5a5a5a5 a5a5a5a5 a5a5a5a5 a5a5a5a5 ................

... ...

010000f0: a5a5a5a5 a5a5a5a5 a5a5a5a5 a5a5a5a5 ................

=> nand write 1000000 0 100000

=> nand read 2000000 0 100000

=> cmp.b 1000000 2000000 100000

Have a great day,
Yiping

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[00lirui]

     Hi.

     Thanks a lot for your solution.

     But what document? I can't get it from CD .

[yipingwang]

Hello Li rui,

I got this method from the QorIQ SDK 1.6 release document, not in MPC8306 BSP release.

If you have problem to run these u-boot commands, please feel free to let me know.

Have a great day,
Yiping

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[00lirui]

the result of command "nand erase chip" like this:

=>nand erase chip

NAND erase:mtdparts variable not set,see "help mtdparts"

Device nor0 not found!

'chip' is not a number

[scottwood]

It's "nand erase.chip" (note the period), not "nand erase chip".

[yipingwang]

You could use the following command instead

nand erase 0 0x100000

Thanks,

Yiping

[catalindemergia]

Hello,

can you tell us

- is it a Freescale board or a custom one ?

- the exact version of CodeWarrior that you are using ?

About the application compile and debug in RAM, use the RAM build configuration.

(you have ROM, RAM and cache build configurations in your wizard-generated project for 8306som)

regards,

Catalin

[00lirui]

The board is Freescale board MPC8306-KIT !