Ethernet to V.35 Implementation using QorIQ processor

[Jijesh]

Hi,
We are developing a Ethernet to V.35 converter system using QorIQ processor (LS1023AXN7KQB). Can you please let us know how to interface V.35 port to QorIQ processor?
Is there any reference design available for this?

Thanks,
Jijesh

[Jijesh]

Hi,

Attached a high level block diagram of our system. We are not clear about where to interface V.35 Transceiver on the LS1023 device. Is there any application reference document available how to use LS1043A/LS1023A QUICC Engine for HDLC, V.35 application.

Thanks,

Jijesh

[yipingwang]

I'm not familiar with V.35.

NXP designs to an attachment unit interface (AUI) specification (MII, GMII, RGMII, SGMII, etc.),
so in most cases, proper operation is achieved if the interface signal requirements (timings, IO levels, etc.) are met.
This includes PHYless designs as well.

Input Output Buffer Information Specification (IBIS) modeling can help determine signal degradation to/from our device across the interconnect.

Actual medium support (copper, fiber, coax, etc) is dependent on the Medium Attachment Unit (MAU) connected to our device (PHY, Switch, FPGA, etc).

LS1046A supports RGMII, 1G SGMII, 2.5G SGMII, QSGMII, and XFI for the Ethernet protocols.
Do you intend to use one of these interfaces?